# Reading c:/program files/Modeltech_xe_starter/win32xoem/../tcl/vsim/pref.tcl # do tester_gen.tdo # ** Warning: (vlib-34) Library already exists at "work". # Model Technology ModelSim XE II vcom 5.8c Compiler 2004.03 Mar 26 2004 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package vital_timing # -- Loading package vcomponents # -- Loading package vital_primitives # -- Loading package textio # -- Loading package vpackage # -- Compiling entity display_enable_gen # -- Compiling architecture structure of display_enable_gen # -- Loading entity x_buf_pp # -- Loading entity x_lut4 # -- Loading entity x_tri_pp # -- Loading entity x_inv # -- Loading entity x_bufgmux # -- Loading entity x_ff # -- Loading entity x_or2 # -- Loading entity x_one # -- Loading entity x_zero # -- Loading package vital_timing # -- Loading entity x_roc # -- Loading entity x_toc # Model Technology ModelSim XE II vcom 5.8c Compiler 2004.03 Mar 26 2004 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package numeric_std # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity tester_gen # -- Compiling architecture testbench_arch of tester_gen # -- Loading package vital_timing # -- Loading package vcomponents # -- Loading package vital_primitives # -- Loading package vpackage # -- Loading entity display_enable_gen # -- Compiling configuration display_enable_gen_cfg # -- Loading entity tester_gen # -- Loading architecture testbench_arch of tester_gen # vsim -lib work -sdfmax /UUT=display_enable_gen_timesim.sdf -t 1ps tester_gen # Loading c:\program files\Modeltech_xe_starter\win32xoem/../std.standard # Loading c:\program files\Modeltech_xe_starter\win32xoem/../ieee.std_logic_1164(body) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../ieee.numeric_std(body) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../std.textio(body) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../ieee.std_logic_textio(body) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../vital2000.vital_timing(body) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../xilinx/vhdl/simprim.vcomponents # Loading c:\program files\Modeltech_xe_starter\win32xoem/../vital2000.vital_primitives(body) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../xilinx/vhdl/simprim.vpackage(body) # Loading work.tester_gen(testbench_arch) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../ieee.vital_timing(body) # Loading work.display_enable_gen(structure) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../xilinx/vhdl/simprim.x_buf_pp(x_buf_pp_v) # Loading display_enable_gen_timesim.sdf # Loading c:\program files\Modeltech_xe_starter\win32xoem/../xilinx/vhdl/simprim.x_lut4(x_lut4_v) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../xilinx/vhdl/simprim.x_tri_pp(x_tri_pp_v) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../xilinx/vhdl/simprim.x_inv(x_inv_v) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../xilinx/vhdl/simprim.x_bufgmux(x_bufgmux_v) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../xilinx/vhdl/simprim.x_ff(x_ff_v) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../xilinx/vhdl/simprim.x_or2(x_or2_v) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../xilinx/vhdl/simprim.x_one(x_one_v) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../xilinx/vhdl/simprim.x_zero(x_zero_v) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../ieee.vital_primitives(body) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../xilinx/vhdl/simprim.x_roc(x_roc_v) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../xilinx/vhdl/simprim.x_toc(x_toc_v) # ** Warning: Design size of 1043 statements or 0 non-Xilinx leaf instances exceeds ModelSim XE-Starter recommended capacity. # Expect performance to be quite adversely affected. # ** Note: (vsim-3587) SDF Backannotation Successfully Completed. # Time: 0 ps Iteration: 0 Region: /tester_gen File: tester_gen.timesim_vhw # .wave # .structure # .signals # ** Failure: Simulation successful (not a failure). No problems detected. # Time: 410 us Iteration: 0 Process: /tester_gen/line__76 File: tester_gen.timesim_vhw # Break at tester_gen.timesim_vhw line 233 # Simulation Breakpoint: Break at tester_gen.timesim_vhw line 233 # MACRO ./tester_gen.tdo PAUSED at line 14