## NOTE: Do not edit this file.
## Auto generated by Project Navigator for VHDL Post-PAR Simulation
##
vlib work
## Compile Post-PAR Model for Module display_enable_gen
vcom -87 -explicit  display_enable_gen_timesim.vhd
vcom -93 -explicit  tester_gen.timesim_vhw
vsim -t 1ps -sdfmax /UUT=display_enable_gen_timesim.sdf  -lib work tester_gen
do tester_gen.udo
view wave
add wave *
view structure
view signals
run -all
## End