JDF G
// Created by Project Navigator ver 1.0
PROJECT tesi
DESIGN tesi
DEVFAM spartan3
DEVFAMTIME 0
DEVICE xc3s200
DEVICETIME 0
DEVPKG ft256
DEVPKGTIME 0
DEVSPEED -4
DEVSPEEDTIME 0
DEVTOPLEVELMODULETYPE HDL
TOPLEVELMODULETYPETIME 0
DEVSYNTHESISTOOL XST (VHDL/Verilog)
SYNTHESISTOOLTIME 0
DEVSIMULATOR Modelsim
SIMULATORTIME 0
DEVGENERATEDSIMULATIONMODEL VHDL
GENERATEDSIMULATIONMODELTIME 0
SOURCE State_logic.vhd
SOURCE frequency_adapter.sch
STIMULUS adapter_tester.tbw
SOURCE display_enable_gen.sch
STIMULUS tester_gen.tbw
[STRATEGY-LIST]
Normal=True