--------------------------------------------------------------------------------
-- Copyright (c) 1995-2003 Xilinx, Inc.
-- All Right Reserved.
--------------------------------------------------------------------------------
--   ____  ____ 
--  /   /\/   / 
-- /___/  \  /    Vendor: Xilinx 
-- \   \   \/     Version : 6.3i
--  \   \         Application : 
--  /   /         Filename : frequency_adapter.vhf
-- /___/   /\     Timestamp : 03/23/2007 10:24:21
-- \   \  /  \ 
--  \___\/\___\ 
--
--Command: 
--Design Name: FTC_MXILINX_frequency_adapter
--

library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
-- synopsys translate_off
library UNISIM;
use UNISIM.Vcomponents.ALL;
-- synopsys translate_on

entity FTC_MXILINX_frequency_adapter is
   port ( C   : in    std_logic; 
          CLR : in    std_logic; 
          T   : in    std_logic; 
          Q   : out   std_logic);
end FTC_MXILINX_frequency_adapter;

architecture BEHAVIORAL of FTC_MXILINX_frequency_adapter is
   attribute BOX_TYPE   : string ;
   attribute INIT       : string ;
   attribute RLOC       : string ;
   signal TQ      : std_logic;
   signal Q_DUMMY : std_logic;
   component XOR2
      port ( I0 : in    std_logic; 
             I1 : in    std_logic; 
             O  : out   std_logic);
   end component;
   attribute BOX_TYPE of XOR2 : component is "BLACK_BOX";
   
   component FDC
      -- synopsys translate_off
      generic( INIT : bit :=  '0');
      -- synopsys translate_on
      port ( C   : in    std_logic; 
             CLR : in    std_logic; 
             D   : in    std_logic; 
             Q   : out   std_logic);
   end component;
   attribute INIT of FDC : component is "0";
   attribute BOX_TYPE of FDC : component is "BLACK_BOX";
   
   attribute RLOC of I_36_35 : label is "X0Y0";
begin
   Q <= Q_DUMMY;
   I_36_32 : XOR2
      port map (I0=>T,      
                I1=>Q_DUMMY,      
                O=>TQ);
   
   I_36_35 : FDC
      port map (C=>C,      
                CLR=>CLR,      
                D=>TQ,      
                Q=>Q_DUMMY);
   
end BEHAVIORAL;


--------------------------------------------------------------------------------
-- Copyright (c) 1995-2003 Xilinx, Inc.
-- All Right Reserved.
--------------------------------------------------------------------------------
--   ____  ____ 
--  /   /\/   / 
-- /___/  \  /    Vendor: Xilinx 
-- \   \   \/     Version : 6.3i
--  \   \         Application : 
--  /   /         Filename : frequency_adapter.vhf
-- /___/   /\     Timestamp : 03/23/2007 10:24:21
-- \   \  /  \ 
--  \___\/\___\ 
--
--Command: 
--Design Name: frequency_adapter
--

library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
-- synopsys translate_off
library UNISIM;
use UNISIM.Vcomponents.ALL;
-- synopsys translate_on

entity frequency_adapter is
   port ( clk       : in    std_logic; 
          clr       : in    std_logic; 
          unofisso  : in    std_logic; 
          clock_out : out   std_logic);
end frequency_adapter;

architecture BEHAVIORAL of frequency_adapter is
   attribute HU_SET     : string ;
   signal XLXN_3    : std_logic;
   signal XLXN_4    : std_logic;
   signal XLXN_5    : std_logic;
   signal XLXN_8    : std_logic;
   signal XLXN_9    : std_logic;
   signal XLXN_15   : std_logic;
   signal XLXN_16   : std_logic;
   signal XLXN_17   : std_logic;
   signal XLXN_21   : std_logic;
   component FTC_MXILINX_frequency_adapter
      port ( C   : in    std_logic; 
             CLR : in    std_logic; 
             T   : in    std_logic; 
             Q   : out   std_logic);
   end component;
   
   attribute HU_SET of XLXI_3 : label is "XLXI_3_0";
   attribute HU_SET of XLXI_4 : label is "XLXI_4_1";
   attribute HU_SET of XLXI_5 : label is "XLXI_5_2";
   attribute HU_SET of XLXI_6 : label is "XLXI_6_3";
   attribute HU_SET of XLXI_7 : label is "XLXI_7_4";
   attribute HU_SET of XLXI_10 : label is "XLXI_10_5";
   attribute HU_SET of XLXI_11 : label is "XLXI_11_6";
   attribute HU_SET of XLXI_12 : label is "XLXI_12_7";
   attribute HU_SET of XLXI_13 : label is "XLXI_13_8";
   attribute HU_SET of XLXI_14 : label is "XLXI_14_9";
begin
   XLXI_3 : FTC_MXILINX_frequency_adapter
      port map (C=>XLXN_4,      
                CLR=>clr,      
                T=>unofisso,      
                Q=>XLXN_5);
   
   XLXI_4 : FTC_MXILINX_frequency_adapter
      port map (C=>XLXN_5,      
                CLR=>clr,      
                T=>unofisso,      
                Q=>XLXN_8);
   
   XLXI_5 : FTC_MXILINX_frequency_adapter
      port map (C=>XLXN_8,      
                CLR=>clr,      
                T=>unofisso,      
                Q=>XLXN_9);
   
   XLXI_6 : FTC_MXILINX_frequency_adapter
      port map (C=>XLXN_3,      
                CLR=>clr,      
                T=>unofisso,      
                Q=>XLXN_4);
   
   XLXI_7 : FTC_MXILINX_frequency_adapter
      port map (C=>clk,      
                CLR=>clr,      
                T=>unofisso,      
                Q=>XLXN_3);
   
   XLXI_10 : FTC_MXILINX_frequency_adapter
      port map (C=>XLXN_9,      
                CLR=>clr,      
                T=>unofisso,      
                Q=>XLXN_15);
   
   XLXI_11 : FTC_MXILINX_frequency_adapter
      port map (C=>XLXN_15,      
                CLR=>clr,      
                T=>unofisso,      
                Q=>XLXN_16);
   
   XLXI_12 : FTC_MXILINX_frequency_adapter
      port map (C=>XLXN_16,      
                CLR=>clr,      
                T=>unofisso,      
                Q=>XLXN_17);
   
   XLXI_13 : FTC_MXILINX_frequency_adapter
      port map (C=>XLXN_17,      
                CLR=>clr,      
                T=>unofisso,      
                Q=>XLXN_21);
   
   XLXI_14 : FTC_MXILINX_frequency_adapter
      port map (C=>XLXN_21,      
                CLR=>clr,      
                T=>unofisso,      
                Q=>clock_out);
   
end BEHAVIORAL;