library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity display_logic is
Port(clk:in std_logic;d1,d2,d3,d4:in std_logic;
end display_logic;

architecture Behavioral of display_logic is

begin


end Behavioral;