-- Xilinx Vhdl netlist produced by netgen application (version G.35)
-- Command       : -intstyle ise -s 4 -pcf display_enable_gen.pcf -ngm display_enable_gen.ngm -rpw 100 -tpw 0 -ar Structure -xon true -w -ofmt vhdl -sim display_enable_gen.ncd display_enable_gen_timesim.vhd 
-- Input file    : display_enable_gen.ncd
-- Output file   : display_enable_gen_timesim.vhd
-- Design name   : display_enable_gen
-- # of Entities : 1
-- Xilinx        : C:/Program Files/Xilinx
-- Device        : 3s200ft256-4 (PRODUCTION 1.32 2004-06-25)

-- This vhdl netlist is a simulation model and uses simulation 
-- primitives which may not represent the true implementation of the 
-- device, however the netlist is functionally correct and should not 
-- be modified. This file cannot be synthesized and should only be used 
-- with supported simulation tools.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library SIMPRIM;
use SIMPRIM.VCOMPONENTS.ALL;
use SIMPRIM.VPACKAGE.ALL;

entity display_enable_gen is
  port (
    clkmezzi : out STD_LOGIC; 
    d3 : out STD_LOGIC; 
    d2 : out STD_LOGIC; 
    d1 : out STD_LOGIC; 
    d0 : out STD_LOGIC; 
    unofisso : in STD_LOGIC := 'X'; 
    clr : in STD_LOGIC := 'X'; 
    clk : in STD_LOGIC := 'X' 
  );
end display_enable_gen;

architecture Structure of display_enable_gen is
  signal clk_BUFGP : STD_LOGIC; 
  signal clr_IBUF : STD_LOGIC; 
  signal unofisso_IBUF : STD_LOGIC; 
  signal clkmezzi_OBUF : STD_LOGIC; 
  signal d0_OBUF : STD_LOGIC; 
  signal clk_BUFGP_IBUFG : STD_LOGIC; 
  signal d1_OBUF : STD_LOGIC; 
  signal d2_OBUF : STD_LOGIC; 
  signal d3_OBUF : STD_LOGIC; 
  signal GLOBAL_LOGIC1 : STD_LOGIC; 
  signal GSR : STD_LOGIC; 
  signal GTS : STD_LOGIC; 
  signal clkmezzi_OBUF_F : STD_LOGIC; 
  signal clkmezzi_OBUF_DYMUX : STD_LOGIC; 
  signal XLXI_6_TQ : STD_LOGIC; 
  signal clkmezzi_OBUF_CLKINV : STD_LOGIC; 
  signal clk_INBUF : STD_LOGIC; 
  signal clr_INBUF : STD_LOGIC; 
  signal clkmezzi_ENABLE : STD_LOGIC; 
  signal clkmezzi_GTS_OR_T : STD_LOGIC; 
  signal clkmezzi_O : STD_LOGIC; 
  signal d0_ENABLE : STD_LOGIC; 
  signal d0_GTS_OR_T : STD_LOGIC; 
  signal d0_O : STD_LOGIC; 
  signal d1_ENABLE : STD_LOGIC; 
  signal d1_GTS_OR_T : STD_LOGIC; 
  signal d1_O : STD_LOGIC; 
  signal d2_ENABLE : STD_LOGIC; 
  signal d2_GTS_OR_T : STD_LOGIC; 
  signal d2_O : STD_LOGIC; 
  signal d3_ENABLE : STD_LOGIC; 
  signal d3_GTS_OR_T : STD_LOGIC; 
  signal d3_O : STD_LOGIC; 
  signal unofisso_INBUF : STD_LOGIC; 
  signal clk_BUFGP_BUFG_S_INVNOT : STD_LOGIC; 
  signal d1_OBUF_F : STD_LOGIC; 
  signal d1_OBUF_G : STD_LOGIC; 
  signal clkmezzi_OBUF_FFY_RST : STD_LOGIC; 
  signal clkmezzi_OBUF_FFY_RSTAND : STD_LOGIC; 
  signal d2_OBUF_G : STD_LOGIC; 
  signal VCC : STD_LOGIC; 
  signal GND : STD_LOGIC; 
begin
  clkmezzi_OBUF_XUSED : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => clkmezzi_OBUF_F,
      O => d0_OBUF
    );
  clkmezzi_OBUF_DYMUX_0 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => XLXI_6_TQ,
      O => clkmezzi_OBUF_DYMUX
    );
  clkmezzi_OBUF_CLKINV_1 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => clk_BUFGP,
      O => clkmezzi_OBUF_CLKINV
    );
  XLXI_6_I_36_32 : X_LUT4
    generic map(
      INIT => X"6666"
    )
    port map (
      ADR0 => unofisso_IBUF,
      ADR1 => clkmezzi_OBUF,
      ADR2 => VCC,
      ADR3 => VCC,
      O => XLXI_6_TQ
    );
  clk_BUFGP_IBUFG_2 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => clk,
      O => clk_INBUF
    );
  clr_IBUF_3 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => clr,
      O => clr_INBUF
    );
  clkmezzi_OBUF_4 : X_TRI_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => clkmezzi_O,
      CTL => clkmezzi_ENABLE,
      O => clkmezzi
    );
  clkmezzi_ENABLEINV : X_INV
    port map (
      I => clkmezzi_GTS_OR_T,
      O => clkmezzi_ENABLE
    );
  clkmezzi_GTS_OR_T_5 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => GTS,
      O => clkmezzi_GTS_OR_T
    );
  d0_OBUF_6 : X_TRI_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => d0_O,
      CTL => d0_ENABLE,
      O => d0
    );
  d0_ENABLEINV : X_INV
    port map (
      I => d0_GTS_OR_T,
      O => d0_ENABLE
    );
  d0_GTS_OR_T_7 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => GTS,
      O => d0_GTS_OR_T
    );
  d1_OBUF_8 : X_TRI_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => d1_O,
      CTL => d1_ENABLE,
      O => d1
    );
  d1_ENABLEINV : X_INV
    port map (
      I => d1_GTS_OR_T,
      O => d1_ENABLE
    );
  d1_GTS_OR_T_9 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => GTS,
      O => d1_GTS_OR_T
    );
  d2_OBUF_10 : X_TRI_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => d2_O,
      CTL => d2_ENABLE,
      O => d2
    );
  d2_ENABLEINV : X_INV
    port map (
      I => d2_GTS_OR_T,
      O => d2_ENABLE
    );
  d2_GTS_OR_T_11 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => GTS,
      O => d2_GTS_OR_T
    );
  d3_OBUF_12 : X_TRI_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => d3_O,
      CTL => d3_ENABLE,
      O => d3
    );
  d3_ENABLEINV : X_INV
    port map (
      I => d3_GTS_OR_T,
      O => d3_ENABLE
    );
  d3_GTS_OR_T_13 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => GTS,
      O => d3_GTS_OR_T
    );
  unofisso_IBUF_14 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => unofisso,
      O => unofisso_INBUF
    );
  clk_BUFGP_BUFG : X_BUFGMUX
    port map (
      I0 => clk_BUFGP_IBUFG,
      I1 => GND,
      S => clk_BUFGP_BUFG_S_INVNOT,
      O => clk_BUFGP,
      GSR => GSR
    );
  clk_BUFGP_BUFG_SINV : X_INV
    port map (
      I => GLOBAL_LOGIC1,
      O => clk_BUFGP_BUFG_S_INVNOT
    );
  d1_OBUF_XUSED : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => d1_OBUF_F,
      O => d1_OBUF
    );
  d1_OBUF_YUSED : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => d1_OBUF_G,
      O => d3_OBUF
    );
  XLXI_6_I_36_35 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => clkmezzi_OBUF_DYMUX,
      CE => VCC,
      CLK => clkmezzi_OBUF_CLKINV,
      SET => GND,
      RST => clkmezzi_OBUF_FFY_RST,
      O => clkmezzi_OBUF
    );
  clkmezzi_OBUF_FFY_RSTOR : X_OR2
    port map (
      I0 => clkmezzi_OBUF_FFY_RSTAND,
      I1 => GSR,
      O => clkmezzi_OBUF_FFY_RST
    );
  clkmezzi_OBUF_FFY_RSTAND_15 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => clr_IBUF,
      O => clkmezzi_OBUF_FFY_RSTAND
    );
  d2_OBUF_YUSED : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => d2_OBUF_G,
      O => d2_OBUF
    );
  XLXI_3_I_36_33 : X_LUT4
    generic map(
      INIT => X"0022"
    )
    port map (
      ADR0 => unofisso_IBUF,
      ADR1 => clkmezzi_OBUF,
      ADR2 => VCC,
      ADR3 => clk_BUFGP,
      O => clkmezzi_OBUF_F
    );
  XLXI_3_I_36_30 : X_LUT4
    generic map(
      INIT => X"8800"
    )
    port map (
      ADR0 => unofisso_IBUF,
      ADR1 => clkmezzi_OBUF,
      ADR2 => VCC,
      ADR3 => clk_BUFGP,
      O => d1_OBUF_G
    );
  XLXI_3_I_36_32 : X_LUT4
    generic map(
      INIT => X"2200"
    )
    port map (
      ADR0 => unofisso_IBUF,
      ADR1 => clkmezzi_OBUF,
      ADR2 => VCC,
      ADR3 => clk_BUFGP,
      O => d1_OBUF_F
    );
  XLXI_3_I_36_31 : X_LUT4
    generic map(
      INIT => X"5000"
    )
    port map (
      ADR0 => clk_BUFGP,
      ADR1 => VCC,
      ADR2 => clkmezzi_OBUF,
      ADR3 => unofisso_IBUF,
      O => d2_OBUF_G
    );
  PWR_VCC_0_LOGICAL_ONE : X_ONE
    port map (
      O => GLOBAL_LOGIC1
    );
  clk_IFF_IMUX : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => clk_INBUF,
      O => clk_BUFGP_IBUFG
    );
  clr_IFF_IMUX : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => clr_INBUF,
      O => clr_IBUF
    );
  clkmezzi_OUTPUT_OFF_OMUX : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => clkmezzi_OBUF,
      O => clkmezzi_O
    );
  d0_OUTPUT_OFF_OMUX : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => d0_OBUF,
      O => d0_O
    );
  d1_OUTPUT_OFF_OMUX : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => d1_OBUF,
      O => d1_O
    );
  d2_OUTPUT_OFF_OMUX : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => d2_OBUF,
      O => d2_O
    );
  d3_OUTPUT_OFF_OMUX : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => d3_OBUF,
      O => d3_O
    );
  unofisso_IFF_IMUX : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => unofisso_INBUF,
      O => unofisso_IBUF
    );
  NlwBlock_display_enable_gen_VCC : X_ONE
    port map (
      O => VCC
    );
  NlwBlock_display_enable_gen_GND : X_ZERO
    port map (
      O => GND
    );
  NlwBlockROC : X_ROC
    generic map (ROC_WIDTH => 100 ns)
    port map (O => GSR);
  NlwBlockTOC : X_TOC
    port map (O => GTS);

end Structure;