Release 6.3i Par G.35
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.

LABINF43::  Fri Mar 23 12:10:41 2007


C:/Program Files/Xilinx/bin/nt/par.exe -w -intstyle ise -ol std -t 1
display_enable_gen_map.ncd display_enable_gen.ncd display_enable_gen.pcf 


Constraints file: display_enable_gen.pcf

Loading device database for application Par from file
"display_enable_gen_map.ncd".
   "display_enable_gen" is an NCD, version 2.38, device xc3s200, package ft256,
speed -4
Loading device for application Par from file '3s200.nph' in environment
C:/Program Files/Xilinx.
Device speed data version:  PRODUCTION 1.32 2004-06-25.


Device utilization summary:

   Number of External IOBs             8 out of 173     4%
      Number of LOCed External IOBs    0 out of 8       0%

   Number of Slices                    3 out of 1920    1%

   Number of BUFGMUXs                  1 out of 8      12%



Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)


Phase 1.1
Phase 1.1 (Checksum:9896a3) REAL time: 0 secs 


Phase 3.3
Phase 3.3 (Checksum:1c9c37d) REAL time: 0 secs 

Phase 4.5
Phase 4.5 (Checksum:26259fc) REAL time: 0 secs 

Phase 5.8
.
Phase 5.8 (Checksum:98a2cd) REAL time: 0 secs 

Phase 6.5
Phase 6.5 (Checksum:39386fa) REAL time: 0 secs 

Phase 7.18
Phase 7.18 (Checksum:42c1d79) REAL time: 0 secs 

Writing design to file display_enable_gen.ncd.

Total REAL time to Placer completion: 0 secs 
Total CPU time to Placer completion: 0 secs 


Phase 1: 23 unrouted;       REAL time: 0 secs 

Phase 2: 21 unrouted;       REAL time: 2 secs 

Phase 3: 0 unrouted;       REAL time: 2 secs 

Phase 4: 0 unrouted;       REAL time: 2 secs 

Total REAL time to Router completion: 2 secs 
Total CPU time to Router completion: 0 secs 

Generating "par" statistics.

**************************
Generating Clock Report
**************************

+-------------------------+----------+------+------+------------+-------------+
|        Clock Net        | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+-------------------------+----------+------+------+------------+-------------+
|         clk_BUFGP       |  BUFGMUX7| No   |    5 |  0.000     |  1.011      |
+-------------------------+----------+------+------+------------+-------------+


   The Delay Summary Report

   The SCORE FOR THIS DESIGN is: 112


The NUMBER OF SIGNALS NOT COMPLETELY ROUTED for this design is: 0

   The AVERAGE CONNECTION DELAY for this design is:        0.969
   The MAXIMUM PIN DELAY IS:                               2.186
   The AVERAGE CONNECTION DELAY on the 10 WORST NETS is:   0.757

   Listing Pin Delays by value: (nsec)

    d < 1.00   < d < 2.00  < d < 3.00  < d < 4.00  < d < 5.00  d >= 5.00
   ---------   ---------   ---------   ---------   ---------   ---------
          14           5           4           0           0           0

Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 6 secs 
Total CPU time to PAR completion: 1 secs 

Peak Memory Usage:  56 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.

Writing design to file display_enable_gen.ncd.


PAR done.