Project Navigator Auto-Make Log File ------------------------------------- Started process "Check Syntax". ========================================================================= * HDL Compilation * ========================================================================= WARNING:HDLParsers:3458 - Because of erroneous VHDL in VHDL file z:\camurati\tesi/State_logic.vhd, automatic determination of correct order of compilation of files in project file state_logic_vhdl.prj is not possible. Please compile your vhdl file(s) individually to find and fix the error(s) in your vhdl file(s). Defaulting to compilation in the order vhdl file names appear in the project file. Compiling vhdl file z:\camurati\tesi/State_logic.vhd in Library work. ERROR:HDLParsers:3011 - z:\camurati\tesi/State_logic.vhd Line 15. End Identifier next_state_logic does not match declaration, state_logic. ERROR:HDLParsers:3010 - z:\camurati\tesi/State_logic.vhd Line 17. Entity state_logic does not exist. ERROR:HDLParsers:3312 - z:\camurati\tesi/State_logic.vhd Line 23. Undefined symbol 'clk'. ERROR:HDLParsers:1209 - z:\camurati\tesi/State_logic.vhd Line 23. clk: Undefined symbol (last report in this block) ERROR:HDLParsers:3312 - z:\camurati\tesi/State_logic.vhd Line 24. Undefined symbol 'std_logic_vector'. ERROR:HDLParsers:1209 - z:\camurati\tesi/State_logic.vhd Line 24. std_logic_vector: Undefined symbol (last report in this block) ERROR:HDLParsers:3313 - z:\camurati\tesi/State_logic.vhd Line 27. Undefined symbol 'clr'. Should it be: cr? ERROR:HDLParsers:1209 - z:\camurati\tesi/State_logic.vhd Line 27. clr: Undefined symbol (last report in this block) ERROR:HDLParsers:3312 - z:\camurati\tesi/State_logic.vhd Line 28. Undefined symbol 'nstate'. ERROR:HDLParsers:1209 - z:\camurati\tesi/State_logic.vhd Line 30. nstate: Undefined symbol (last report in this block) ERROR:HDLParsers:3312 - z:\camurati\tesi/State_logic.vhd Line 30. Undefined symbol 'state_in'. ERROR:HDLParsers:1209 - z:\camurati\tesi/State_logic.vhd Line 30. state_in: Undefined symbol (last report in this block) ERROR:HDLParsers:3312 - z:\camurati\tesi/State_logic.vhd Line 33. Undefined symbol 'state_out'. WARNING:HDLParsers:1406 - z:\camurati\tesi/State_logic.vhd Line 23. No sensitivity list and no wait in the process ERROR:HDLParsers:164 - z:\camurati\tesi/State_logic.vhd Line 36. parse error, unexpected $, expecting SEMICOLON WARNING:HDLParsers:3465 - Library as no units. Did not save reference file xst/work/hdllib.ref for it. ERROR: XST failed Process "Check Syntax" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Check Syntax". ========================================================================= * HDL Compilation * ========================================================================= WARNING:HDLParsers:3458 - Because of erroneous VHDL in VHDL file z:\camurati\tesi/State_logic.vhd, automatic determination of correct order of compilation of files in project file state_logic_vhdl.prj is not possible. Please compile your vhdl file(s) individually to find and fix the error(s) in your vhdl file(s). Defaulting to compilation in the order vhdl file names appear in the project file. Compiling vhdl file z:\camurati\tesi/State_logic.vhd in Library work. ERROR:HDLParsers:164 - z:\camurati\tesi/State_logic.vhd Line 36. parse error, unexpected $, expecting SEMICOLON ERROR: XST failed Process "Check Syntax" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Check Syntax". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file z:/camurati/tesi/State_logic.vhd in Library work. Entity (Architecture ) compiled. Completed process "Check Syntax". Project Navigator Auto-Make Log File ------------------------------------- Started process "Create Schematic Symbol". Compiling vhdl file z:/camurati/tesi/State_logic.vhd in Library work. Entity (Architecture ) compiled. tdtfi(vhdl) completed successfully. Release 6.3i - spl2sym G.35 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. Completed process "Create Schematic Symbol". Project Navigator Auto-Make Log File ------------------------------------- Started process "View VHDL Functional Model". Release 6.3i - sch2vhdl G.35 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. DRC Check completed: No Error found. Vhdl netlist file generated. Completed process "View VHDL Functional Model". Project Navigator Auto-Make Log File ------------------------------------- Started process "Create Schematic Symbol". Release 6.3i - sch2sym G.35 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. Completed process "Create Schematic Symbol". Project Navigator Auto-Make Log File ------------------------------------- Launching Application for process "Generate Expected Simulation Results". Reading c:/program files/Modeltech_xe_starter/win32xoem/../tcl/vsim/pref.tcl # 5.8c # do adapter_tester.ado listening on address 127.0.0.1 port 1200 # resume # Model Technology ModelSim XE II vcom 5.8c Compiler 2004.03 Mar 26 2004 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package numeric_std # -- Loading package vital_timing # -- Loading package vcomponents # -- Compiling entity ftc_mxilinx_frequency_adapter # -- Compiling architecture behavioral of ftc_mxilinx_frequency_adapter # -- Loading entity xor2 # -- Loading entity fdc # -- Compiling entity frequency_adapter # -- Compiling architecture behavioral of frequency_adapter # -- Loading entity ftc_mxilinx_frequency_adapter # Model Technology ModelSim XE II vcom 5.8c Compiler 2004.03 Mar 26 2004 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package numeric_std # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity adapter_tester # -- Compiling architecture testbench_arch of adapter_tester # -- Loading package vital_timing # -- Loading package vcomponents # -- Loading entity frequency_adapter # -- Compiling configuration frequency_adapter_cfg # -- Loading entity adapter_tester # -- Loading architecture testbench_arch of adapter_tester # vsim -lib work -t 1ps adapter_tester # Loading c:\program files\Modeltech_xe_starter\win32xoem/../std.standard # Loading c:\program files\Modeltech_xe_starter\win32xoem/../ieee.std_logic_1164(body) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../ieee.numeric_std(body) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../std.textio(body) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../ieee.std_logic_textio(body) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../ieee.vital_timing(body) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../xilinx/vhdl/unisim.vcomponents # Loading work.adapter_tester(testbench_arch) # Loading work.frequency_adapter(behavioral) # Loading work.ftc_mxilinx_frequency_adapter(behavioral) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../xilinx/vhdl/unisim.xor2(xor2_v) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../xilinx/vhdl/unisim.fdc(fdc_v) # ** Failure: Success! Simulation for annotation completed # Time: 100 us Iteration: 0 Process: /adapter_tester/line__79 File: adapter_tester.ant # Break at adapter_tester.ant line 92 # Stopped at adapter_tester.ant line 92 Project Navigator Auto-Make Log File ------------------------------------- Started process "View VHDL Functional Model". Release 6.3i - sch2vhdl G.35 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. DRC Check completed: No Error found. Vhdl netlist file generated. Completed process "View VHDL Functional Model". Project Navigator Auto-Make Log File ------------------------------------- Launching Application for process "Generate Expected Simulation Results". Reading c:/program files/Modeltech_xe_starter/win32xoem/../tcl/vsim/pref.tcl # 5.8c # do tester_gen.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.8c Compiler 2004.03 Mar 26 2004 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package numeric_std # -- Loading package vital_timing # -- Loading package vcomponents # -- Compiling entity ftc_mxilinx_display_enable_gen # -- Compiling architecture behavioral of ftc_mxilinx_display_enable_gen # -- Loading entity xor2 # -- Loading entity fdc # -- Compiling entity d2_4e_mxilinx_display_enable_gen # -- Compiling architecture behavioral of d2_4e_mxilinx_display_enable_gen # -- Loading entity and3 # -- Loading entity and3b1 # -- Loading entity and3b2 # -- Compiling entity display_enable_gen # -- Compiling architecture behavioral of display_enable_gen # -- Loading entity d2_4e_mxilinx_display_enable_gen # -- Loading entity ftc_mxilinx_display_enable_gen # -- Loading entity vcc # Model Technology ModelSim XE II vcom 5.8c Compiler 2004.03 Mar 26 2004 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package numeric_std # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity tester_gen # -- Compiling architecture testbench_arch of tester_gen # -- Loading package vital_timing # -- Loading package vcomponents # -- Loading entity display_enable_gen # -- Compiling configuration display_enable_gen_cfg # -- Loading entity tester_gen # -- Loading architecture testbench_arch of tester_gen # vsim -lib work -t 1ps tester_gen # Loading c:\program files\Modeltech_xe_starter\win32xoem/../std.standard # Loading c:\program files\Modeltech_xe_starter\win32xoem/../ieee.std_logic_1164(body) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../ieee.numeric_std(body) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../std.textio(body) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../ieee.std_logic_textio(body) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../ieee.vital_timing(body) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../xilinx/vhdl/unisim.vcomponents # Loading work.tester_gen(testbench_arch) # Loading work.display_enable_gen(behavioral) # Loading work.d2_4e_mxilinx_display_enable_gen(behavioral) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../xilinx/vhdl/unisim.and3(and3_v) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../xilinx/vhdl/unisim.and3b1(and3b1_v) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../xilinx/vhdl/unisim.and3b2(and3b2_v) # Loading work.ftc_mxilinx_display_enable_gen(behavioral) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../xilinx/vhdl/unisim.xor2(xor2_v) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../xilinx/vhdl/unisim.fdc(fdc_v) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../xilinx/vhdl/unisim.vcc(vcc_v) # ** Failure: Success! Simulation for annotation completed # Time: 100 us Iteration: 0 Process: /tester_gen/line__136 File: tester_gen.ant # Break at tester_gen.ant line 148 # Stopped at tester_gen.ant line 148 Project Navigator Auto-Make Log File ------------------------------------- Started process "View VHDL Functional Model". Release 6.3i - sch2vhdl G.35 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. DRC Check completed: No Error found. Vhdl netlist file generated. Completed process "View VHDL Functional Model". Compiling vhdl file z:/camurati/tesi/display_enable_gen.vhf in Library work. Entity (Architecture ) compiled. Entity (Architecture ) compiled. Entity (Architecture ) compiled. Launching Application for process "Generate Expected Simulation Results". Reading c:/program files/Modeltech_xe_starter/win32xoem/../tcl/vsim/pref.tcl # 5.8c # do tester_gen.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.8c Compiler 2004.03 Mar 26 2004 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package numeric_std # -- Loading package vital_timing # -- Loading package vcomponents # -- Compiling entity ftc_mxilinx_display_enable_gen # -- Compiling architecture behavioral of ftc_mxilinx_display_enable_gen # -- Loading entity xor2 # -- Loading entity fdc # -- Compiling entity d2_4e_mxilinx_display_enable_gen # -- Compiling architecture behavioral of d2_4e_mxilinx_display_enable_gen # -- Loading entity and3 # -- Loading entity and3b1 # -- Loading entity and3b2 # -- Compiling entity display_enable_gen # -- Compiling architecture behavioral of display_enable_gen # -- Loading entity d2_4e_mxilinx_display_enable_gen # -- Loading entity ftc_mxilinx_display_enable_gen # -- Loading entity vcc # Model Technology ModelSim XE II vcom 5.8c Compiler 2004.03 Mar 26 2004 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package numeric_std # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity tester_gen # -- Compiling architecture testbench_arch of tester_gen # -- Loading package vital_timing # -- Loading package vcomponents # -- Loading entity display_enable_gen # -- Compiling configuration display_enable_gen_cfg # -- Loading entity tester_gen # -- Loading architecture testbench_arch of tester_gen # vsim -lib work -t 1ps tester_gen # Loading c:\program files\Modeltech_xe_starter\win32xoem/../std.standard # Loading c:\program files\Modeltech_xe_starter\win32xoem/../ieee.std_logic_1164(body) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../ieee.numeric_std(body) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../std.textio(body) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../ieee.std_logic_textio(body) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../ieee.vital_timing(body) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../xilinx/vhdl/unisim.vcomponents # Loading work.tester_gen(testbench_arch) # Loading work.display_enable_gen(behavioral) # Loading work.d2_4e_mxilinx_display_enable_gen(behavioral) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../xilinx/vhdl/unisim.and3(and3_v) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../xilinx/vhdl/unisim.and3b1(and3b1_v) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../xilinx/vhdl/unisim.and3b2(and3b2_v) # Loading work.ftc_mxilinx_display_enable_gen(behavioral) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../xilinx/vhdl/unisim.xor2(xor2_v) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../xilinx/vhdl/unisim.fdc(fdc_v) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../xilinx/vhdl/unisim.vcc(vcc_v) # ** Failure: Success! Simulation for annotation completed # Time: 100 us Iteration: 0 Process: /tester_gen/line__136 File: tester_gen.ant # Break at tester_gen.ant line 148 # Stopped at tester_gen.ant line 148 Project Navigator Auto-Make Log File ------------------------------------- Launching Application for process "Generate Expected Simulation Results". Reading c:/program files/Modeltech_xe_starter/win32xoem/../tcl/vsim/pref.tcl # 5.8c # do tester_gen.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.8c Compiler 2004.03 Mar 26 2004 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package numeric_std # -- Loading package vital_timing # -- Loading package vcomponents # -- Compiling entity ftc_mxilinx_display_enable_gen # -- Compiling architecture behavioral of ftc_mxilinx_display_enable_gen # -- Loading entity xor2 # -- Loading entity fdc # -- Compiling entity d2_4e_mxilinx_display_enable_gen # -- Compiling architecture behavioral of d2_4e_mxilinx_display_enable_gen # -- Loading entity and3 # -- Loading entity and3b1 # -- Loading entity and3b2 # -- Compiling entity display_enable_gen # -- Compiling architecture behavioral of display_enable_gen # -- Loading entity d2_4e_mxilinx_display_enable_gen # -- Loading entity ftc_mxilinx_display_enable_gen # -- Loading entity vcc # Model Technology ModelSim XE II vcom 5.8c Compiler 2004.03 Mar 26 2004 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package numeric_std # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity tester_gen # -- Compiling architecture testbench_arch of tester_gen # -- Loading package vital_timing # -- Loading package vcomponents # -- Loading entity display_enable_gen # -- Compiling configuration display_enable_gen_cfg # -- Loading entity tester_gen # -- Loading architecture testbench_arch of tester_gen # vsim -lib work -t 1ps tester_gen # Loading c:\program files\Modeltech_xe_starter\win32xoem/../std.standard # Loading c:\program files\Modeltech_xe_starter\win32xoem/../ieee.std_logic_1164(body) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../ieee.numeric_std(body) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../std.textio(body) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../ieee.std_logic_textio(body) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../ieee.vital_timing(body) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../xilinx/vhdl/unisim.vcomponents # Loading work.tester_gen(testbench_arch) # Loading work.display_enable_gen(behavioral) # Loading work.d2_4e_mxilinx_display_enable_gen(behavioral) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../xilinx/vhdl/unisim.and3(and3_v) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../xilinx/vhdl/unisim.and3b1(and3b1_v) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../xilinx/vhdl/unisim.and3b2(and3b2_v) # Loading work.ftc_mxilinx_display_enable_gen(behavioral) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../xilinx/vhdl/unisim.xor2(xor2_v) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../xilinx/vhdl/unisim.fdc(fdc_v) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../xilinx/vhdl/unisim.vcc(vcc_v) # ** Failure: Success! Simulation for annotation completed # Time: 110 us Iteration: 0 Process: /tester_gen/line__136 File: tester_gen.ant # Break at tester_gen.ant line 148 # Stopped at tester_gen.ant line 148 Project Navigator Auto-Make Log File ------------------------------------- Started process "View VHDL Functional Model". Release 6.3i - sch2vhdl G.35 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. ERROR:DesignEntry:77 - Net "lento" is connected to input ports and instance output pins. A net cannot be connected to both input ports and instance output pins ERROR:DesignEntry:77 - Net "veloce" is connected to input ports and instance output pins. A net cannot be connected to both input ports and instance output pins ERROR:DesignEntry:77 - Net "medio" is connected to input ports and instance output pins. A net cannot be connected to both input ports and instance output pins Error: Process "View VHDL Functional Model" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "View VHDL Functional Model". Release 6.3i - sch2vhdl G.35 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. ERROR:DesignEntry:77 - Net "lento" is connected to input ports and instance output pins. A net cannot be connected to both input ports and instance output pins ERROR:DesignEntry:77 - Net "veloce" is connected to input ports and instance output pins. A net cannot be connected to both input ports and instance output pins ERROR:DesignEntry:77 - Net "medio" is connected to input ports and instance output pins. A net cannot be connected to both input ports and instance output pins Error: Process "View VHDL Functional Model" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "View VHDL Functional Model". Release 6.3i - sch2vhdl G.35 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. ERROR:DesignEntry:77 - Net "lento" is connected to input ports and instance output pins. A net cannot be connected to both input ports and instance output pins ERROR:DesignEntry:77 - Net "veloce" is connected to input ports and instance output pins. A net cannot be connected to both input ports and instance output pins ERROR:DesignEntry:77 - Net "medio" is connected to input ports and instance output pins. A net cannot be connected to both input ports and instance output pins Error: Process "View VHDL Functional Model" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "View VHDL Functional Model". Release 6.3i - sch2vhdl G.35 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. ERROR:DesignEntry:77 - Net "lento" is connected to input ports and instance output pins. A net cannot be connected to both input ports and instance output pins ERROR:DesignEntry:77 - Net "veloce" is connected to input ports and instance output pins. A net cannot be connected to both input ports and instance output pins ERROR:DesignEntry:77 - Net "medio" is connected to input ports and instance output pins. A net cannot be connected to both input ports and instance output pins Error: Process "View VHDL Functional Model" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "View VHDL Functional Model". Release 6.3i - sch2vhdl G.35 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. DRC Check completed: No Error found. Vhdl netlist file generated. Completed process "View VHDL Functional Model". Project Navigator Auto-Make Log File ------------------------------------- Launching Application for process "Generate Expected Simulation Results". Reading c:/program files/Modeltech_xe_starter/win32xoem/../tcl/vsim/pref.tcl # 5.8c # do tester_gen.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.8c Compiler 2004.03 Mar 26 2004 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package numeric_std # -- Loading package vital_timing # -- Loading package vcomponents # -- Compiling entity ftc_mxilinx_display_enable_gen # -- Compiling architecture behavioral of ftc_mxilinx_display_enable_gen # -- Loading entity xor2 # -- Loading entity fdc # -- Compiling entity d2_4e_mxilinx_display_enable_gen # -- Compiling architecture behavioral of d2_4e_mxilinx_display_enable_gen # -- Loading entity and3 # -- Loading entity and3b1 # -- Loading entity and3b2 # -- Compiling entity display_enable_gen # -- Compiling architecture behavioral of display_enable_gen # -- Loading entity d2_4e_mxilinx_display_enable_gen # -- Loading entity ftc_mxilinx_display_enable_gen # -- Loading entity vcc # Model Technology ModelSim XE II vcom 5.8c Compiler 2004.03 Mar 26 2004 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package numeric_std # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity tester_gen # -- Compiling architecture testbench_arch of tester_gen # -- Loading package vital_timing # -- Loading package vcomponents # -- Loading entity display_enable_gen # -- Compiling configuration display_enable_gen_cfg # -- Loading entity tester_gen # -- Loading architecture testbench_arch of tester_gen # vsim -lib work -t 1ps tester_gen # Loading c:\program files\Modeltech_xe_starter\win32xoem/../std.standard # Loading c:\program files\Modeltech_xe_starter\win32xoem/../ieee.std_logic_1164(body) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../ieee.numeric_std(body) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../std.textio(body) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../ieee.std_logic_textio(body) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../ieee.vital_timing(body) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../xilinx/vhdl/unisim.vcomponents # Loading work.tester_gen(testbench_arch) # Loading work.display_enable_gen(behavioral) # Loading work.d2_4e_mxilinx_display_enable_gen(behavioral) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../xilinx/vhdl/unisim.and3(and3_v) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../xilinx/vhdl/unisim.and3b1(and3b1_v) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../xilinx/vhdl/unisim.and3b2(and3b2_v) # Loading work.ftc_mxilinx_display_enable_gen(behavioral) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../xilinx/vhdl/unisim.xor2(xor2_v) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../xilinx/vhdl/unisim.fdc(fdc_v) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../xilinx/vhdl/unisim.vcc(vcc_v) # ** Failure: Success! Simulation for annotation completed # Time: 100 us Iteration: 0 Process: /tester_gen/line__196 File: tester_gen.ant # Break at tester_gen.ant line 208 # Stopped at tester_gen.ant line 208 Project Navigator Auto-Make Log File ------------------------------------- Started process "View VHDL Functional Model". Release 6.3i - sch2vhdl G.35 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. DRC Check completed: No Error found. Vhdl netlist file generated. Completed process "View VHDL Functional Model". Project Navigator Auto-Make Log File ------------------------------------- Launching Application for process "Generate Expected Simulation Results". Reading c:/program files/Modeltech_xe_starter/win32xoem/../tcl/vsim/pref.tcl # 5.8c # do tester_gen.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.8c Compiler 2004.03 Mar 26 2004 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package numeric_std # -- Loading package vital_timing # -- Loading package vcomponents # -- Compiling entity ftc_mxilinx_display_enable_gen # -- Compiling architecture behavioral of ftc_mxilinx_display_enable_gen # -- Loading entity xor2 # -- Loading entity fdc # -- Compiling entity d2_4e_mxilinx_display_enable_gen # -- Compiling architecture behavioral of d2_4e_mxilinx_display_enable_gen # -- Loading entity and3 # -- Loading entity and3b1 # -- Loading entity and3b2 # -- Compiling entity display_enable_gen # -- Compiling architecture behavioral of display_enable_gen # -- Loading entity d2_4e_mxilinx_display_enable_gen # -- Loading entity ftc_mxilinx_display_enable_gen # Model Technology ModelSim XE II vcom 5.8c Compiler 2004.03 Mar 26 2004 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package numeric_std # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity tester_gen # -- Compiling architecture testbench_arch of tester_gen # -- Loading package vital_timing # -- Loading package vcomponents # -- Loading entity display_enable_gen # -- Compiling configuration display_enable_gen_cfg # -- Loading entity tester_gen # -- Loading architecture testbench_arch of tester_gen # vsim -lib work -t 1ps tester_gen # Loading c:\program files\Modeltech_xe_starter\win32xoem/../std.standard # Loading c:\program files\Modeltech_xe_starter\win32xoem/../ieee.std_logic_1164(body) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../ieee.numeric_std(body) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../std.textio(body) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../ieee.std_logic_textio(body) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../ieee.vital_timing(body) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../xilinx/vhdl/unisim.vcomponents # Loading work.tester_gen(testbench_arch) # Loading work.display_enable_gen(behavioral) # Loading work.d2_4e_mxilinx_display_enable_gen(behavioral) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../xilinx/vhdl/unisim.and3(and3_v) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../xilinx/vhdl/unisim.and3b1(and3b1_v) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../xilinx/vhdl/unisim.and3b2(and3b2_v) # Loading work.ftc_mxilinx_display_enable_gen(behavioral) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../xilinx/vhdl/unisim.xor2(xor2_v) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../xilinx/vhdl/unisim.fdc(fdc_v) # ** Failure: Success! Simulation for annotation completed # Time: 100 us Iteration: 0 Process: /tester_gen/line__199 File: tester_gen.ant # Break at tester_gen.ant line 212 # Stopped at tester_gen.ant line 212 Project Navigator Auto-Make Log File ------------------------------------- Launching Application for process "Generate Expected Simulation Results". Reading c:/program files/Modeltech_xe_starter/win32xoem/../tcl/vsim/pref.tcl # 5.8c # do tester_gen.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.8c Compiler 2004.03 Mar 26 2004 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package numeric_std # -- Loading package vital_timing # -- Loading package vcomponents # -- Compiling entity ftc_mxilinx_display_enable_gen # -- Compiling architecture behavioral of ftc_mxilinx_display_enable_gen # -- Loading entity xor2 # -- Loading entity fdc # -- Compiling entity d2_4e_mxilinx_display_enable_gen # -- Compiling architecture behavioral of d2_4e_mxilinx_display_enable_gen # -- Loading entity and3 # -- Loading entity and3b1 # -- Loading entity and3b2 # -- Compiling entity display_enable_gen # -- Compiling architecture behavioral of display_enable_gen # -- Loading entity d2_4e_mxilinx_display_enable_gen # -- Loading entity ftc_mxilinx_display_enable_gen # Model Technology ModelSim XE II vcom 5.8c Compiler 2004.03 Mar 26 2004 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package numeric_std # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity tester_gen # -- Compiling architecture testbench_arch of tester_gen # -- Loading package vital_timing # -- Loading package vcomponents # -- Loading entity display_enable_gen # -- Compiling configuration display_enable_gen_cfg # -- Loading entity tester_gen # -- Loading architecture testbench_arch of tester_gen # vsim -lib work -t 1ps tester_gen # Loading c:\program files\Modeltech_xe_starter\win32xoem/../std.standard # Loading c:\program files\Modeltech_xe_starter\win32xoem/../ieee.std_logic_1164(body) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../ieee.numeric_std(body) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../std.textio(body) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../ieee.std_logic_textio(body) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../ieee.vital_timing(body) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../xilinx/vhdl/unisim.vcomponents # Loading work.tester_gen(testbench_arch) # Loading work.display_enable_gen(behavioral) # Loading work.d2_4e_mxilinx_display_enable_gen(behavioral) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../xilinx/vhdl/unisim.and3(and3_v) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../xilinx/vhdl/unisim.and3b1(and3b1_v) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../xilinx/vhdl/unisim.and3b2(and3b2_v) # Loading work.ftc_mxilinx_display_enable_gen(behavioral) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../xilinx/vhdl/unisim.xor2(xor2_v) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../xilinx/vhdl/unisim.fdc(fdc_v) # ** Failure: Success! Simulation for annotation completed # Time: 410 us Iteration: 0 Process: /tester_gen/line__199 File: tester_gen.ant # Break at tester_gen.ant line 222 # Stopped at tester_gen.ant line 222 Project Navigator Auto-Make Log File ------------------------------------- Launching Application for process "Generate Expected Simulation Results". Reading c:/program files/Modeltech_xe_starter/win32xoem/../tcl/vsim/pref.tcl # 5.8c # do tester_gen.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.8c Compiler 2004.03 Mar 26 2004 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package numeric_std # -- Loading package vital_timing # -- Loading package vcomponents # -- Compiling entity ftc_mxilinx_display_enable_gen # -- Compiling architecture behavioral of ftc_mxilinx_display_enable_gen # -- Loading entity xor2 # -- Loading entity fdc # -- Compiling entity d2_4e_mxilinx_display_enable_gen # -- Compiling architecture behavioral of d2_4e_mxilinx_display_enable_gen # -- Loading entity and3 # -- Loading entity and3b1 # -- Loading entity and3b2 # -- Compiling entity display_enable_gen # -- Compiling architecture behavioral of display_enable_gen # -- Loading entity d2_4e_mxilinx_display_enable_gen # -- Loading entity ftc_mxilinx_display_enable_gen # Model Technology ModelSim XE II vcom 5.8c Compiler 2004.03 Mar 26 2004 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package numeric_std # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity tester_gen # -- Compiling architecture testbench_arch of tester_gen # -- Loading package vital_timing # -- Loading package vcomponents # -- Loading entity display_enable_gen # -- Compiling configuration display_enable_gen_cfg # -- Loading entity tester_gen # -- Loading architecture testbench_arch of tester_gen # vsim -lib work -t 1ps tester_gen # Loading c:\program files\Modeltech_xe_starter\win32xoem/../std.standard # Loading c:\program files\Modeltech_xe_starter\win32xoem/../ieee.std_logic_1164(body) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../ieee.numeric_std(body) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../std.textio(body) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../ieee.std_logic_textio(body) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../ieee.vital_timing(body) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../xilinx/vhdl/unisim.vcomponents # Loading work.tester_gen(testbench_arch) # Loading work.display_enable_gen(behavioral) # Loading work.d2_4e_mxilinx_display_enable_gen(behavioral) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../xilinx/vhdl/unisim.and3(and3_v) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../xilinx/vhdl/unisim.and3b1(and3b1_v) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../xilinx/vhdl/unisim.and3b2(and3b2_v) # Loading work.ftc_mxilinx_display_enable_gen(behavioral) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../xilinx/vhdl/unisim.xor2(xor2_v) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../xilinx/vhdl/unisim.fdc(fdc_v) # ** Failure: Success! Simulation for annotation completed # Time: 410 ms Iteration: 0 Process: /tester_gen/line__199 File: tester_gen.ant # Break at tester_gen.ant line 222 # Stopped at tester_gen.ant line 222 Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file z:/camurati/tesi/display_enable_gen.vhf in Library work. Architecture behavioral of Entity ftc_mxilinx_display_enable_gen is up to date. Architecture behavioral of Entity d2_4e_mxilinx_display_enable_gen is up to date. Architecture behavioral of Entity display_enable_gen is up to date. ========================================================================= * HDL Analysis * ========================================================================= Analyzing Entity (Architecture ). Set user-defined property "HU_SET = XLXI_3_0" for instance in unit . Set user-defined property "HU_SET = XLXI_4_1" for instance in unit . Set user-defined property "HU_SET = XLXI_5_2" for instance in unit . Set user-defined property "HU_SET = XLXI_6_3" for instance in unit . Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Set user-defined property "INIT = 0" for instance in unit . Set user-defined property "RLOC = X0Y0" for instance in unit . Entity analyzed. Unit generated. ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is z:/camurati/tesi/display_enable_gen.vhf. Unit synthesized. Synthesizing Unit . Related source file is z:/camurati/tesi/display_enable_gen.vhf. Unit synthesized. Synthesizing Unit . Related source file is z:/camurati/tesi/display_enable_gen.vhf. Unit synthesized. ========================================================================= * Advanced HDL Synthesis * ========================================================================= Advanced RAM inference ... Advanced multiplier inference ... Advanced Registered AddSub inference ... Dynamic shift register inference ... ========================================================================= HDL Synthesis Report Found no macro ========================================================================= ========================================================================= * Low Level Synthesis * ========================================================================= Optimizing unit ... Optimizing unit ... Optimizing unit ... Loading device for application Xst from file '3s200.nph' in environment C:/Program Files/Xilinx. Mapping all equations... Building and optimizing final netlist ... Found area constraint ratio of 100 (+ 5) on block display_enable_gen, actual ratio is 0. ========================================================================= * Final Report * ========================================================================= Device utilization summary: --------------------------- Selected Device : 3s200ft256-4 Number of Slices: 3 out of 1920 0% Number of Slice Flip Flops: 3 out of 3840 0% Number of bonded IOBs: 9 out of 173 5% Number of GCLKs: 1 out of 8 12% ========================================================================= TIMING REPORT Clock Information: ------------------ -----------------------------------+------------------------+-------+ Clock Signal | Clock buffer(FF name) | Load | -----------------------------------+------------------------+-------+ XLXI_5/I_36_35:Q | NONE | 1 | XLXI_4/I_36_35:Q | NONE | 1 | clk | BUFGP | 1 | -----------------------------------+------------------------+-------+ Timing Summary: --------------- Speed Grade: -4 Minimum period: 2.431ns (Maximum Frequency: 411.353MHz) Minimum input arrival time before clock: 3.501ns Maximum output required time after clock: 7.103ns Maximum combinational path delay: No path found ========================================================================= Completed process "Synthesize". Started process "Translate". Command Line: ngdbuild -intstyle ise -dd z:\camurati\tesi/_ngo -i -p xc3s200-ft256-4 display_enable_gen.ngc display_enable_gen.ngd Reading NGO file "z:/camurati/tesi/display_enable_gen.ngc" ... Reading component libraries for design expansion... Checking timing specifications ... Checking expanded design ... NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0 Total memory usage is 38140 kilobytes Writing NGD file "display_enable_gen.ngd" ... Writing NGDBUILD log file "display_enable_gen.bld"... NGDBUILD done. Completed process "Translate". Started process "Map". Using target part "3s200ft256-4". Removing unused or disabled logic... Running cover... Running directed packing... Running delay-based LUT packing... Running related packing... Design Summary: Number of errors: 0 Number of warnings: 0 Logic Utilization: Number of Slice Flip Flops: 3 out of 3,840 1% Number of 4 input LUTs: 7 out of 3,840 1% Logic Distribution: Number of occupied Slices: 4 out of 1,920 1% Number of Slices containing only related logic: 4 out of 4 100% Number of Slices containing unrelated logic: 0 out of 4 0% *See NOTES below for an explanation of the effects of unrelated logic Total Number of 4 input LUTs: 7 out of 3,840 1% Number of bonded IOBs: 10 out of 173 5% Number of GCLKs: 1 out of 8 12% Total equivalent gate count for design: 69 Additional JTAG gate count for IOBs: 480 Peak Memory Usage: 66 MB NOTES: Related logic is defined as being logic that shares connectivity - e.g. two LUTs are "related" if they share common inputs. When assembling slices, Map gives priority to combine logic that is related. Doing so results in the best timing performance. Unrelated logic shares no connectivity. Map will only begin packing unrelated logic into a slice once 99% of the slices are occupied through related logic packing. Note that once logic distribution reaches the 99% level through related logic packing, this does not mean the device is completely utilized. Unrelated logic packing will then begin, continuing until all usable LUTs and FFs are occupied. Depending on your timing budget, increased levels of unrelated logic packing may adversely affect the overall timing performance of your design. Mapping completed. See MAP report file "display_enable_gen_map.mrp" for details. Completed process "Map". Mapping Module display_enable_gen . . . MAP command line: map -intstyle ise -p xc3s200-ft256-4 -cm area -pr b -k 4 -c 100 -tx off -o display_enable_gen_map.ncd display_enable_gen.ngd display_enable_gen.pcf Mapping Module display_enable_gen: DONE Started process "Place & Route". Constraints file: display_enable_gen.pcf Loading device database for application Par from file "display_enable_gen_map.ncd". "display_enable_gen" is an NCD, version 2.38, device xc3s200, package ft256, speed -4 Loading device for application Par from file '3s200.nph' in environment C:/Program Files/Xilinx. Device speed data version: PRODUCTION 1.32 2004-06-25. Resolving physical constraints. Finished resolving physical constraints. Device utilization summary: Number of External IOBs 10 out of 173 5% Number of LOCed External IOBs 0 out of 10 0% Number of Slices 4 out of 1920 1% Number of BUFGMUXs 1 out of 8 12% Overall effort level (-ol): Standard (set by user) Placer effort level (-pl): Standard (set by user) Placer cost table entry (-t): 1 Router effort level (-rl): Standard (set by user) Phase 1.1 Phase 1.1 (Checksum:9896ac) REAL time: 2 secs Phase 3.3 Phase 3.3 (Checksum:1c9c37d) REAL time: 2 secs Phase 4.5 Phase 4.5 (Checksum:26259fc) REAL time: 2 secs Phase 5.8 . Phase 5.8 (Checksum:98a651) REAL time: 2 secs Phase 6.5 Phase 6.5 (Checksum:39386fa) REAL time: 2 secs Phase 7.18 Phase 7.18 (Checksum:42c1d79) REAL time: 2 secs Writing design to file display_enable_gen.ncd. Total REAL time to Placer completion: 2 secs Total CPU time to Placer completion: 0 secs Phase 1: 33 unrouted; REAL time: 2 secs Phase 2: 31 unrouted; REAL time: 2 secs Phase 3: 3 unrouted; REAL time: 2 secs Phase 4: 0 unrouted; REAL time: 2 secs Total REAL time to Router completion: 2 secs Total CPU time to Router completion: 1 secs Generating "par" statistics. ************************** Generating Clock Report ************************** +-------------------------+----------+------+------+------------+-------------+ | Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)| +-------------------------+----------+------+------+------------+-------------+ | clk_BUFGP | BUFGMUX7| No | 1 | 0.000 | 1.010 | +-------------------------+----------+------+------+------------+-------------+ | veloce_OBUF | Local | | 7 | 0.000 | 1.172 | +-------------------------+----------+------+------+------------+-------------+ | medio_OBUF | Local | | 7 | 0.000 | 1.973 | +-------------------------+----------+------+------+------------+-------------+ Generating Pad Report. All signals are completely routed. Total REAL time to PAR completion: 6 secs Total CPU time to PAR completion: 1 secs Peak Memory Usage: 56 MB Placement: Completed - No errors found. Routing: Completed - No errors found. Writing design to file display_enable_gen.ncd. PAR done. Completed process "Place & Route". Started process "Generate Post-Place & Route Static Timing". Analysis completed Fri Mar 23 11:46:46 2007 -------------------------------------------------------------------------------- Generating Report ... Completed process "Generate Post-Place & Route Static Timing". Place & Route Module display_enable_gen . . . PAR command line: par -w -intstyle ise -ol std -t 1 display_enable_gen_map.ncd display_enable_gen.ncd display_enable_gen.pcf PAR completed successfully Started process "Generate Post-Place & Route Simulation Model". Completed process "Generate Post-Place & Route Simulation Model". Compiling vhdl file z:/camurati/tesi/display_enable_gen.vhf in Library work. Entity (Architecture ) compiled. Entity (Architecture ) compiled. Entity (Architecture ) compiled. Project Navigator Auto-Make Log File ------------------------------------- Compiling vhdl file z:/camurati/tesi/display_enable_gen.vhf in Library work. Entity (Architecture ) compiled. Entity (Architecture ) compiled. Entity (Architecture ) compiled. Project Navigator Auto-Make Log File ------------------------------------- Compiling vhdl file z:/camurati/tesi/display_enable_gen.vhf in Library work. Entity (Architecture ) compiled. Entity (Architecture ) compiled. Entity (Architecture ) compiled. Project Navigator Auto-Make Log File ------------------------------------- Started process "View VHDL Functional Model". Release 6.3i - sch2vhdl G.35 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. DRC Check completed: No Error found. Vhdl netlist file generated. Completed process "View VHDL Functional Model". Compiling vhdl file z:/camurati/tesi/display_enable_gen.vhf in Library work. Entity (Architecture ) compiled. Entity (Architecture ) compiled. ERROR:HDLParsers:856 - z:/camurati/tesi/display_enable_gen.vhf Line 248. No default value for unconnected port . ERROR:HDLParsers:900 - z:/camurati/tesi/display_enable_gen.vhf Line 259. The label XLXI_5 is not declared. Launching Application for process "Generate Expected Simulation Results". Reading c:/program files/Modeltech_xe_starter/win32xoem/../tcl/vsim/pref.tcl # 5.8c # do tester_gen.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.8c Compiler 2004.03 Mar 26 2004 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package numeric_std # -- Loading package vital_timing # -- Loading package vcomponents # -- Compiling entity ftc_mxilinx_display_enable_gen # -- Compiling architecture behavioral of ftc_mxilinx_display_enable_gen # -- Loading entity xor2 # -- Loading entity fdc # -- Compiling entity d2_4e_mxilinx_display_enable_gen # -- Compiling architecture behavioral of d2_4e_mxilinx_display_enable_gen # -- Loading entity and3 # -- Loading entity and3b1 # -- Loading entity and3b2 # -- Compiling entity display_enable_gen # -- Compiling architecture behavioral of display_enable_gen # -- Loading entity d2_4e_mxilinx_display_enable_gen # -- Loading entity ftc_mxilinx_display_enable_gen # ** Error: display_enable_gen.vhf(251): No actual specified for c. # ** Error: display_enable_gen.vhf(259): VHDL Compiler exiting # ** Error: c:/program files/Modeltech_xe_starter/win32xoem/vcom failed. # Executing ONERROR command at macro ./tester_gen.ado line 10 ERROR: VSim failed to simulate annotated testbench Project Navigator Auto-Make Log File ------------------------------------- Launching Application for process "Generate Expected Simulation Results". Reading c:/program files/Modeltech_xe_starter/win32xoem/../tcl/vsim/pref.tcl # 5.8c # do tester_gen.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.8c Compiler 2004.03 Mar 26 2004 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package numeric_std # -- Loading package vital_timing # -- Loading package vcomponents # -- Compiling entity ftc_mxilinx_display_enable_gen # -- Compiling architecture behavioral of ftc_mxilinx_display_enable_gen # -- Loading entity xor2 # -- Loading entity fdc # -- Compiling entity d2_4e_mxilinx_display_enable_gen # -- Compiling architecture behavioral of d2_4e_mxilinx_display_enable_gen # -- Loading entity and3 # -- Loading entity and3b1 # -- Loading entity and3b2 # -- Compiling entity display_enable_gen # -- Compiling architecture behavioral of display_enable_gen # -- Loading entity d2_4e_mxilinx_display_enable_gen # -- Loading entity ftc_mxilinx_display_enable_gen # ** Error: display_enable_gen.vhf(251): No actual specified for c. # ** Error: display_enable_gen.vhf(259): VHDL Compiler exiting # ** Error: c:/program files/Modeltech_xe_starter/win32xoem/vcom failed. # Executing ONERROR command at macro ./tester_gen.ado line 10 ERROR: VSim failed to simulate annotated testbench Project Navigator Auto-Make Log File ------------------------------------- Started process "View VHDL Functional Model". Release 6.3i - sch2vhdl G.35 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. DRC Check completed: No Error found. Vhdl netlist file generated. Completed process "View VHDL Functional Model". Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file z:/camurati/tesi/display_enable_gen.vhf in Library work. Architecture behavioral of Entity ftc_mxilinx_display_enable_gen is up to date. Architecture behavioral of Entity d2_4e_mxilinx_display_enable_gen is up to date. Architecture behavioral of Entity display_enable_gen is up to date. ========================================================================= * HDL Analysis * ========================================================================= Analyzing Entity (Architecture ). Set user-defined property "HU_SET = XLXI_3_0" for instance in unit . Set user-defined property "HU_SET = XLXI_6_1" for instance in unit . Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Set user-defined property "INIT = 0" for instance in unit . Set user-defined property "RLOC = X0Y0" for instance in unit . Entity analyzed. Unit generated. ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is z:/camurati/tesi/display_enable_gen.vhf. Unit synthesized. Synthesizing Unit . Related source file is z:/camurati/tesi/display_enable_gen.vhf. Unit synthesized. Synthesizing Unit . Related source file is z:/camurati/tesi/display_enable_gen.vhf. Unit synthesized. ========================================================================= * Advanced HDL Synthesis * ========================================================================= Advanced RAM inference ... Advanced multiplier inference ... Advanced Registered AddSub inference ... Dynamic shift register inference ... ========================================================================= HDL Synthesis Report Found no macro ========================================================================= ========================================================================= * Low Level Synthesis * ========================================================================= Optimizing unit ... Optimizing unit ... Optimizing unit ... Loading device for application Xst from file '3s200.nph' in environment C:/Program Files/Xilinx. Mapping all equations... Building and optimizing final netlist ... Found area constraint ratio of 100 (+ 5) on block display_enable_gen, actual ratio is 0. ========================================================================= * Final Report * ========================================================================= Device utilization summary: --------------------------- Selected Device : 3s200ft256-4 Number of Slices: 1 out of 1920 0% Number of Slice Flip Flops: 1 out of 3840 0% Number of bonded IOBs: 7 out of 173 4% Number of GCLKs: 1 out of 8 12% ========================================================================= TIMING REPORT Clock Information: ------------------ -----------------------------------+------------------------+-------+ Clock Signal | Clock buffer(FF name) | Load | -----------------------------------+------------------------+-------+ clk | BUFGP | 1 | -----------------------------------+------------------------+-------+ Timing Summary: --------------- Speed Grade: -4 Minimum period: 2.402ns (Maximum Frequency: 416.320MHz) Minimum input arrival time before clock: 3.164ns Maximum output required time after clock: 7.074ns Maximum combinational path delay: 6.444ns ========================================================================= Completed process "Synthesize". Started process "Translate". Command Line: ngdbuild -intstyle ise -dd z:\camurati\tesi/_ngo -i -p xc3s200-ft256-4 display_enable_gen.ngc display_enable_gen.ngd Reading NGO file "z:/camurati/tesi/display_enable_gen.ngc" ... Reading component libraries for design expansion... Checking timing specifications ... Checking expanded design ... NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0 Total memory usage is 38140 kilobytes Writing NGD file "display_enable_gen.ngd" ... Writing NGDBUILD log file "display_enable_gen.bld"... NGDBUILD done. Completed process "Translate". Started process "Map". Using target part "3s200ft256-4". Removing unused or disabled logic... Running cover... Running directed packing... Running delay-based LUT packing... Running related packing... Design Summary: Number of errors: 0 Number of warnings: 1 Logic Utilization: Number of Slice Flip Flops: 1 out of 3,840 1% Number of 4 input LUTs: 3 out of 3,840 1% Logic Distribution: Number of occupied Slices: 2 out of 1,920 1% Number of Slices containing only related logic: 2 out of 2 100% Number of Slices containing unrelated logic: 0 out of 2 0% *See NOTES below for an explanation of the effects of unrelated logic Total Number of 4 input LUTs: 3 out of 3,840 1% Number of bonded IOBs: 8 out of 173 4% Number of GCLKs: 1 out of 8 12% Total equivalent gate count for design: 29 Additional JTAG gate count for IOBs: 384 Peak Memory Usage: 66 MB NOTES: Related logic is defined as being logic that shares connectivity - e.g. two LUTs are "related" if they share common inputs. When assembling slices, Map gives priority to combine logic that is related. Doing so results in the best timing performance. Unrelated logic shares no connectivity. Map will only begin packing unrelated logic into a slice once 99% of the slices are occupied through related logic packing. Note that once logic distribution reaches the 99% level through related logic packing, this does not mean the device is completely utilized. Unrelated logic packing will then begin, continuing until all usable LUTs and FFs are occupied. Depending on your timing budget, increased levels of unrelated logic packing may adversely affect the overall timing performance of your design. Mapping completed. See MAP report file "display_enable_gen_map.mrp" for details. Completed process "Map". Mapping Module display_enable_gen . . . MAP command line: map -intstyle ise -p xc3s200-ft256-4 -cm area -pr b -k 4 -c 100 -tx off -o display_enable_gen_map.ncd display_enable_gen.ngd display_enable_gen.pcf Mapping Module display_enable_gen: DONE Started process "Place & Route". Constraints file: display_enable_gen.pcf Loading device database for application Par from file "display_enable_gen_map.ncd". "display_enable_gen" is an NCD, version 2.38, device xc3s200, package ft256, speed -4 Loading device for application Par from file '3s200.nph' in environment C:/Program Files/Xilinx. Device speed data version: PRODUCTION 1.32 2004-06-25. Resolving physical constraints. Finished resolving physical constraints. Device utilization summary: Number of External IOBs 8 out of 173 4% Number of LOCed External IOBs 0 out of 8 0% Number of Slices 2 out of 1920 1% Number of BUFGMUXs 1 out of 8 12% Overall effort level (-ol): Standard (set by user) Placer effort level (-pl): Standard (set by user) Placer cost table entry (-t): 1 Router effort level (-rl): Standard (set by user) Phase 1.1 Phase 1.1 (Checksum:9896a0) REAL time: 0 secs . Phase 3.3 Phase 3.3 (Checksum:1c9c37d) REAL time: 0 secs Phase 4.5 Phase 4.5 (Checksum:26259fc) REAL time: 0 secs Phase 5.8 . Phase 5.8 (Checksum:98c68b) REAL time: 0 secs Phase 6.5 Phase 6.5 (Checksum:39386fa) REAL time: 0 secs Phase 7.18 Phase 7.18 (Checksum:42c1d79) REAL time: 0 secs Writing design to file display_enable_gen.ncd. Total REAL time to Placer completion: 0 secs Total CPU time to Placer completion: 0 secs Phase 1: 15 unrouted; REAL time: 0 secs Phase 2: 13 unrouted; REAL time: 0 secs Phase 3: 2 unrouted; REAL time: 0 secs Phase 4: 0 unrouted; REAL time: 0 secs Total REAL time to Router completion: 0 secs Total CPU time to Router completion: 0 secs Generating "par" statistics. ************************** Generating Clock Report ************************** +-------------------------+----------+------+------+------------+-------------+ | Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)| +-------------------------+----------+------+------+------------+-------------+ | clk_BUFGP | BUFGMUX0| No | 3 | 0.000 | 1.011 | +-------------------------+----------+------+------+------------+-------------+ Generating Pad Report. All signals are completely routed. Total REAL time to PAR completion: 5 secs Total CPU time to PAR completion: 1 secs Peak Memory Usage: 55 MB Placement: Completed - No errors found. Routing: Completed - No errors found. Writing design to file display_enable_gen.ncd. PAR done. Completed process "Place & Route". Started process "Generate Post-Place & Route Static Timing". Analysis completed Fri Mar 23 11:59:57 2007 -------------------------------------------------------------------------------- Generating Report ... Completed process "Generate Post-Place & Route Static Timing". Place & Route Module display_enable_gen . . . PAR command line: par -w -intstyle ise -ol std -t 1 display_enable_gen_map.ncd display_enable_gen.ncd display_enable_gen.pcf PAR completed successfully Started process "Generate Post-Place & Route Simulation Model". Completed process "Generate Post-Place & Route Simulation Model". Compiling vhdl file z:/camurati/tesi/display_enable_gen.vhf in Library work. Entity (Architecture ) compiled. Entity (Architecture ) compiled. Entity (Architecture ) compiled. Project Navigator Auto-Make Log File ------------------------------------- Started process "View VHDL Functional Model". Release 6.3i - sch2vhdl G.35 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. DRC Check completed: No Error found. Vhdl netlist file generated. Completed process "View VHDL Functional Model". Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file z:/camurati/tesi/display_enable_gen.vhf in Library work. Architecture behavioral of Entity ftc_mxilinx_display_enable_gen is up to date. Architecture behavioral of Entity d2_4e_mxilinx_display_enable_gen is up to date. Architecture behavioral of Entity display_enable_gen is up to date. ========================================================================= * HDL Analysis * ========================================================================= Analyzing Entity (Architecture ). Set user-defined property "HU_SET = XLXI_3_0" for instance in unit . Set user-defined property "HU_SET = XLXI_6_1" for instance in unit . Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Set user-defined property "INIT = 0" for instance in unit . Set user-defined property "RLOC = X0Y0" for instance in unit . Entity analyzed. Unit generated. ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is z:/camurati/tesi/display_enable_gen.vhf. Unit synthesized. Synthesizing Unit . Related source file is z:/camurati/tesi/display_enable_gen.vhf. Unit synthesized. Synthesizing Unit . Related source file is z:/camurati/tesi/display_enable_gen.vhf. Unit synthesized. ========================================================================= * Advanced HDL Synthesis * ========================================================================= Advanced RAM inference ... Advanced multiplier inference ... Advanced Registered AddSub inference ... Dynamic shift register inference ... ========================================================================= HDL Synthesis Report Found no macro ========================================================================= ========================================================================= * Low Level Synthesis * ========================================================================= Optimizing unit ... Optimizing unit ... Optimizing unit ... Loading device for application Xst from file '3s200.nph' in environment C:/Program Files/Xilinx. Mapping all equations... Building and optimizing final netlist ... Found area constraint ratio of 100 (+ 5) on block display_enable_gen, actual ratio is 0. ========================================================================= * Final Report * ========================================================================= Device utilization summary: --------------------------- Selected Device : 3s200ft256-4 Number of Slices: 1 out of 1920 0% Number of Slice Flip Flops: 1 out of 3840 0% Number of bonded IOBs: 7 out of 173 4% Number of GCLKs: 1 out of 8 12% ========================================================================= TIMING REPORT Clock Information: ------------------ -----------------------------------+------------------------+-------+ Clock Signal | Clock buffer(FF name) | Load | -----------------------------------+------------------------+-------+ clk | BUFGP | 1 | -----------------------------------+------------------------+-------+ Timing Summary: --------------- Speed Grade: -4 Minimum period: 2.402ns (Maximum Frequency: 416.320MHz) Minimum input arrival time before clock: 3.582ns Maximum output required time after clock: 7.074ns Maximum combinational path delay: 8.254ns ========================================================================= Completed process "Synthesize". Started process "Translate". Command Line: ngdbuild -intstyle ise -dd z:\camurati\tesi/_ngo -i -p xc3s200-ft256-4 display_enable_gen.ngc display_enable_gen.ngd Reading NGO file "z:/camurati/tesi/display_enable_gen.ngc" ... Reading component libraries for design expansion... Checking timing specifications ... Checking expanded design ... NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0 Total memory usage is 38140 kilobytes Writing NGD file "display_enable_gen.ngd" ... Writing NGDBUILD log file "display_enable_gen.bld"... NGDBUILD done. Completed process "Translate". Started process "Map". Using target part "3s200ft256-4". Removing unused or disabled logic... Running cover... Running directed packing... Running delay-based LUT packing... Running related packing... Design Summary: Number of errors: 0 Number of warnings: 1 Logic Utilization: Number of Slice Flip Flops: 1 out of 3,840 1% Number of 4 input LUTs: 5 out of 3,840 1% Logic Distribution: Number of occupied Slices: 3 out of 1,920 1% Number of Slices containing only related logic: 3 out of 3 100% Number of Slices containing unrelated logic: 0 out of 3 0% *See NOTES below for an explanation of the effects of unrelated logic Total Number of 4 input LUTs: 5 out of 3,840 1% Number of bonded IOBs: 8 out of 173 4% Number of GCLKs: 1 out of 8 12% Total equivalent gate count for design: 41 Additional JTAG gate count for IOBs: 384 Peak Memory Usage: 66 MB NOTES: Related logic is defined as being logic that shares connectivity - e.g. two LUTs are "related" if they share common inputs. When assembling slices, Map gives priority to combine logic that is related. Doing so results in the best timing performance. Unrelated logic shares no connectivity. Map will only begin packing unrelated logic into a slice once 99% of the slices are occupied through related logic packing. Note that once logic distribution reaches the 99% level through related logic packing, this does not mean the device is completely utilized. Unrelated logic packing will then begin, continuing until all usable LUTs and FFs are occupied. Depending on your timing budget, increased levels of unrelated logic packing may adversely affect the overall timing performance of your design. Mapping completed. See MAP report file "display_enable_gen_map.mrp" for details. Completed process "Map". Mapping Module display_enable_gen . . . MAP command line: map -intstyle ise -p xc3s200-ft256-4 -cm area -pr b -k 4 -c 100 -tx off -o display_enable_gen_map.ncd display_enable_gen.ngd display_enable_gen.pcf Mapping Module display_enable_gen: DONE Started process "Place & Route". Constraints file: display_enable_gen.pcf Loading device database for application Par from file "display_enable_gen_map.ncd". "display_enable_gen" is an NCD, version 2.38, device xc3s200, package ft256, speed -4 Loading device for application Par from file '3s200.nph' in environment C:/Program Files/Xilinx. Device speed data version: PRODUCTION 1.32 2004-06-25. Resolving physical constraints. Finished resolving physical constraints. Device utilization summary: Number of External IOBs 8 out of 173 4% Number of LOCed External IOBs 0 out of 8 0% Number of Slices 3 out of 1920 1% Number of BUFGMUXs 1 out of 8 12% Overall effort level (-ol): Standard (set by user) Placer effort level (-pl): Standard (set by user) Placer cost table entry (-t): 1 Router effort level (-rl): Standard (set by user) Phase 1.1 Phase 1.1 (Checksum:9896a3) REAL time: 0 secs Phase 3.3 Phase 3.3 (Checksum:1c9c37d) REAL time: 0 secs Phase 4.5 Phase 4.5 (Checksum:26259fc) REAL time: 0 secs Phase 5.8 . Phase 5.8 (Checksum:98a2cd) REAL time: 0 secs Phase 6.5 Phase 6.5 (Checksum:39386fa) REAL time: 0 secs Phase 7.18 Phase 7.18 (Checksum:42c1d79) REAL time: 0 secs Writing design to file display_enable_gen.ncd. Total REAL time to Placer completion: 0 secs Total CPU time to Placer completion: 0 secs Phase 1: 23 unrouted; REAL time: 0 secs Phase 2: 21 unrouted; REAL time: 0 secs Phase 3: 0 unrouted; REAL time: 0 secs Phase 4: 0 unrouted; REAL time: 0 secs Total REAL time to Router completion: 0 secs Total CPU time to Router completion: 0 secs Generating "par" statistics. ************************** Generating Clock Report ************************** +-------------------------+----------+------+------+------------+-------------+ | Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)| +-------------------------+----------+------+------+------------+-------------+ | clk_BUFGP | BUFGMUX7| No | 5 | 0.000 | 1.011 | +-------------------------+----------+------+------+------------+-------------+ Generating Pad Report. All signals are completely routed. Total REAL time to PAR completion: 5 secs Total CPU time to PAR completion: 1 secs Peak Memory Usage: 56 MB Placement: Completed - No errors found. Routing: Completed - No errors found. Writing design to file display_enable_gen.ncd. PAR done. Completed process "Place & Route". Started process "Generate Post-Place & Route Static Timing". Analysis completed Fri Mar 23 12:03:45 2007 -------------------------------------------------------------------------------- Generating Report ... Completed process "Generate Post-Place & Route Static Timing". Place & Route Module display_enable_gen . . . PAR command line: par -w -intstyle ise -ol std -t 1 display_enable_gen_map.ncd display_enable_gen.ncd display_enable_gen.pcf PAR completed successfully Started process "Generate Post-Place & Route Simulation Model". Completed process "Generate Post-Place & Route Simulation Model". Compiling vhdl file z:/camurati/tesi/display_enable_gen.vhf in Library work. Entity (Architecture ) compiled. Entity (Architecture ) compiled. Entity (Architecture ) compiled. Project Navigator Auto-Make Log File ------------------------------------- Started process "View VHDL Functional Model". Release 6.3i - sch2vhdl G.35 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. ERROR:DesignEntry:99 - I/O Marker at (1216, 480) is not connected to anything. Error: Process "View VHDL Functional Model" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "View VHDL Functional Model". Release 6.3i - sch2vhdl G.35 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. ERROR:DesignEntry:99 - I/O Marker at (1216, 480) is not connected to anything. Error: Process "View VHDL Functional Model" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "View VHDL Functional Model". Release 6.3i - sch2vhdl G.35 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. DRC Check completed: No Error found. Vhdl netlist file generated. Completed process "View VHDL Functional Model". Project Navigator Auto-Make Log File ------------------------------------- Started process "View VHDL Functional Model". Release 6.3i - sch2vhdl G.35 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. ERROR:DesignEntry:77 - Net "clkmezzi" is connected to input ports and instance output pins. A net cannot be connected to both input ports and instance output pins Error: Process "View VHDL Functional Model" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "View VHDL Functional Model". Release 6.3i - sch2vhdl G.35 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. DRC Check completed: No Error found. Vhdl netlist file generated. Completed process "View VHDL Functional Model". Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file z:/camurati/tesi/display_enable_gen.vhf in Library work. Architecture behavioral of Entity ftc_mxilinx_display_enable_gen is up to date. Architecture behavioral of Entity d2_4e_mxilinx_display_enable_gen is up to date. Architecture behavioral of Entity display_enable_gen is up to date. ========================================================================= * HDL Analysis * ========================================================================= Analyzing Entity (Architecture ). Set user-defined property "HU_SET = XLXI_3_0" for instance in unit . Set user-defined property "HU_SET = XLXI_6_1" for instance in unit . Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Set user-defined property "INIT = 0" for instance in unit . Set user-defined property "RLOC = X0Y0" for instance in unit . Entity analyzed. Unit generated. ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is z:/camurati/tesi/display_enable_gen.vhf. Unit synthesized. Synthesizing Unit . Related source file is z:/camurati/tesi/display_enable_gen.vhf. Unit synthesized. Synthesizing Unit . Related source file is z:/camurati/tesi/display_enable_gen.vhf. Unit synthesized. ========================================================================= * Advanced HDL Synthesis * ========================================================================= Advanced RAM inference ... Advanced multiplier inference ... Advanced Registered AddSub inference ... Dynamic shift register inference ... ========================================================================= HDL Synthesis Report Found no macro ========================================================================= ========================================================================= * Low Level Synthesis * ========================================================================= Optimizing unit ... Optimizing unit ... Optimizing unit ... Loading device for application Xst from file '3s200.nph' in environment C:/Program Files/Xilinx. Mapping all equations... Building and optimizing final netlist ... Found area constraint ratio of 100 (+ 5) on block display_enable_gen, actual ratio is 0. ========================================================================= * Final Report * ========================================================================= Device utilization summary: --------------------------- Selected Device : 3s200ft256-4 Number of Slices: 1 out of 1920 0% Number of Slice Flip Flops: 1 out of 3840 0% Number of bonded IOBs: 7 out of 173 4% Number of GCLKs: 1 out of 8 12% ========================================================================= TIMING REPORT Clock Information: ------------------ -----------------------------------+------------------------+-------+ Clock Signal | Clock buffer(FF name) | Load | -----------------------------------+------------------------+-------+ clk | BUFGP | 1 | -----------------------------------+------------------------+-------+ Timing Summary: --------------- Speed Grade: -4 Minimum period: 2.402ns (Maximum Frequency: 416.320MHz) Minimum input arrival time before clock: 3.582ns Maximum output required time after clock: 7.074ns Maximum combinational path delay: 8.254ns ========================================================================= Completed process "Synthesize". Started process "Translate". Command Line: ngdbuild -intstyle ise -dd z:\camurati\tesi/_ngo -i -p xc3s200-ft256-4 display_enable_gen.ngc display_enable_gen.ngd Reading NGO file "z:/camurati/tesi/display_enable_gen.ngc" ... Reading component libraries for design expansion... Checking timing specifications ... Checking expanded design ... NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0 Total memory usage is 38140 kilobytes Writing NGD file "display_enable_gen.ngd" ... Writing NGDBUILD log file "display_enable_gen.bld"... NGDBUILD done. Completed process "Translate". Started process "Map". Using target part "3s200ft256-4". Removing unused or disabled logic... Running cover... Running directed packing... Running delay-based LUT packing... Running related packing... Design Summary: Number of errors: 0 Number of warnings: 1 Logic Utilization: Number of Slice Flip Flops: 1 out of 3,840 1% Number of 4 input LUTs: 5 out of 3,840 1% Logic Distribution: Number of occupied Slices: 3 out of 1,920 1% Number of Slices containing only related logic: 3 out of 3 100% Number of Slices containing unrelated logic: 0 out of 3 0% *See NOTES below for an explanation of the effects of unrelated logic Total Number of 4 input LUTs: 5 out of 3,840 1% Number of bonded IOBs: 8 out of 173 4% Number of GCLKs: 1 out of 8 12% Total equivalent gate count for design: 41 Additional JTAG gate count for IOBs: 384 Peak Memory Usage: 66 MB NOTES: Related logic is defined as being logic that shares connectivity - e.g. two LUTs are "related" if they share common inputs. When assembling slices, Map gives priority to combine logic that is related. Doing so results in the best timing performance. Unrelated logic shares no connectivity. Map will only begin packing unrelated logic into a slice once 99% of the slices are occupied through related logic packing. Note that once logic distribution reaches the 99% level through related logic packing, this does not mean the device is completely utilized. Unrelated logic packing will then begin, continuing until all usable LUTs and FFs are occupied. Depending on your timing budget, increased levels of unrelated logic packing may adversely affect the overall timing performance of your design. Mapping completed. See MAP report file "display_enable_gen_map.mrp" for details. Completed process "Map". Mapping Module display_enable_gen . . . MAP command line: map -intstyle ise -p xc3s200-ft256-4 -cm area -pr b -k 4 -c 100 -tx off -o display_enable_gen_map.ncd display_enable_gen.ngd display_enable_gen.pcf Mapping Module display_enable_gen: DONE Started process "Place & Route". Constraints file: display_enable_gen.pcf Loading device database for application Par from file "display_enable_gen_map.ncd". "display_enable_gen" is an NCD, version 2.38, device xc3s200, package ft256, speed -4 Loading device for application Par from file '3s200.nph' in environment C:/Program Files/Xilinx. Device speed data version: PRODUCTION 1.32 2004-06-25. Resolving physical constraints. Finished resolving physical constraints. Device utilization summary: Number of External IOBs 8 out of 173 4% Number of LOCed External IOBs 0 out of 8 0% Number of Slices 3 out of 1920 1% Number of BUFGMUXs 1 out of 8 12% Overall effort level (-ol): Standard (set by user) Placer effort level (-pl): Standard (set by user) Placer cost table entry (-t): 1 Router effort level (-rl): Standard (set by user) Phase 1.1 Phase 1.1 (Checksum:9896a3) REAL time: 0 secs Phase 3.3 Phase 3.3 (Checksum:1c9c37d) REAL time: 0 secs Phase 4.5 Phase 4.5 (Checksum:26259fc) REAL time: 0 secs Phase 5.8 . Phase 5.8 (Checksum:98a2cd) REAL time: 0 secs Phase 6.5 Phase 6.5 (Checksum:39386fa) REAL time: 0 secs Phase 7.18 Phase 7.18 (Checksum:42c1d79) REAL time: 0 secs Writing design to file display_enable_gen.ncd. Total REAL time to Placer completion: 0 secs Total CPU time to Placer completion: 0 secs Phase 1: 23 unrouted; REAL time: 0 secs Phase 2: 21 unrouted; REAL time: 2 secs Phase 3: 0 unrouted; REAL time: 2 secs Phase 4: 0 unrouted; REAL time: 2 secs Total REAL time to Router completion: 2 secs Total CPU time to Router completion: 0 secs Generating "par" statistics. ************************** Generating Clock Report ************************** +-------------------------+----------+------+------+------------+-------------+ | Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)| +-------------------------+----------+------+------+------------+-------------+ | clk_BUFGP | BUFGMUX7| No | 5 | 0.000 | 1.011 | +-------------------------+----------+------+------+------------+-------------+ Generating Pad Report. All signals are completely routed. Total REAL time to PAR completion: 6 secs Total CPU time to PAR completion: 1 secs Peak Memory Usage: 56 MB Placement: Completed - No errors found. Routing: Completed - No errors found. Writing design to file display_enable_gen.ncd. PAR done. Completed process "Place & Route". Started process "Generate Post-Place & Route Static Timing". Analysis completed Fri Mar 23 12:10:47 2007 -------------------------------------------------------------------------------- Generating Report ... Completed process "Generate Post-Place & Route Static Timing". Place & Route Module display_enable_gen . . . PAR command line: par -w -intstyle ise -ol std -t 1 display_enable_gen_map.ncd display_enable_gen.ncd display_enable_gen.pcf PAR completed successfully Started process "Generate Post-Place & Route Simulation Model". Completed process "Generate Post-Place & Route Simulation Model". Compiling vhdl file z:/camurati/tesi/display_enable_gen.vhf in Library work. Entity (Architecture ) compiled. Entity (Architecture ) compiled. Entity (Architecture ) compiled. Project Navigator Auto-Make Log File ------------------------------------- Started process "Create Schematic Symbol". Release 6.3i - sch2sym G.35 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. Completed process "Create Schematic Symbol".