library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity score is
	port(	C1,C2,C3,C4: in  std_logic_vector (3 downto 0);
         	L0,L1,L2,L3: out std_logic
	);
end score;

architecture structural of score is 

	component bubblesort4
		port(	C1,C2,C3,C4: in  std_logic_vector (3 downto 0);
         		C1o,C2o,C3o,C4o: out std_logic_vector (3 downto 0)
		);
	end component;
	
	component compute_score
		port(	C1,C2,C3,C4: in std_logic_vector (3 downto 0);
			L0,L1,L2,L3: out std_logic
		);
	end component;
	signal carta1,carta2,carta3,carta4: std_logic_vector (3 downto 0);
begin
	bubblesort:bubblesort4
		port map(C1,C2,C3,C4,carta1,carta2,carta3,carta4);
	computescore:compute_score
		port map(carta1,carta2,carta3,carta4,L0,L1,L2,L3);
end structural;