library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity compute_score is
	port(	C1,C2,C3,C4: in  std_logic_vector (3 downto 0);
         	L0,L1,L2,L3: out std_logic
	);
end compute_score;

architecture structural of compute_score is 

	component and_bin
		port (	A,B,C,D: in  std_logic_vector(3 downto 0);
          		O1,O2,O3:    out std_logic
          	     );
	end component;
	
	component compute
		port (	A,B,C: in  std_logic;
          		P,T,DC,CO:    out std_logic
		      );
	end component;
	component compute_led
		port (	P,T,DC,CO:  in  std_logic;
          		L0,L1,L2,L3:out std_logic
		);
	end component;
	signal a,b,c,p,t,dc,co: std_logic;
begin
	andbin:and_bin
		port map(C1,C2,C3,C4,a,b,c);
	comp:compute
		port map(a,b,c,p,t,dc,co);
	computeled:compute_led
		port map(p,t,dc,co,L0,L1,L2,L3);
end structural;