library ieee;
use ieee.std_logic_1164.all;

entity compute is
    port (A,B,C: in  std_logic;
          P,T,DC,CO:    out std_logic);
end compute;


architecture logic of compute  is
begin
	P  <= A and B and C;
	T  <= (A and B) or (B and C);
	DC <= A and C;
	CO <= A or B or C;
end logic;