library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity bubblesort4 is
	port(	C1,C2,C3,C4: in  std_logic_vector (3 downto 0);
         	C1o,C2o,C3o,C4o: out std_logic_vector (3 downto 0)
	);
end bubblesort4;

architecture structural of bubblesort4 is 

	component comparator
		port(	A, B: in  std_logic_vector (3 downto 0);
        	 	C, D: out std_logic_vector (3 downto 0)
    		);
	end component;

	signal c30out_1,c30out_2,c31out_1,c31out_2,c32out_1,c20out_1,c20out_2,c21out_1 : std_logic_vector (3 downto 0);
begin
	c3_0:comparator
		port map(C1,C2,c30out_1,c30out_2);
	c3_1:comparator
		port map(c30out_2,C3,c31out_1,c31out_2);
	c3_2:comparator
		port map(c31out_2,C4,c32out_1,C4o);
	c2_0:comparator
		port map(c30out_1,c31out_1,c20out_1,c20out_2);
	c2_1:comparator
		port map(c20out_2,c32out_1,c21out_1,C3o);
	c1_0:comparator
		port map(c20out_1,c21out_1,C1o,C2o);
end structural;