library ieee;
use ieee.std_logic_1164.all;

entity and_bin is
    port (A,B,C,D: in  std_logic_vector(3 downto 0);
          O1,O2,O3:    out std_logic
          );
end and_bin;

architecture structural of and_bin is
	component and_2 
		port (	A, B: in  std_logic;
        		O:    out std_logic
		);
	end component;
	component and_4 
		port (	A, B, C, D: in  std_logic;
        		O:    out std_logic
		);
	end component;

signal uno1,due1,tre1,quattro1 : std_logic;
signal uno2,due2,tre2,quattro2 : std_logic;
signal uno3,due3,tre3,quattro3 : std_logic;
begin
	a2_1: and_2
		port map(A(0),B(0),uno1);
	a2_2: and_2
		port map(A(1),B(1),due1);
	a2_3: and_2
		port map(A(2),B(2),tre1);
	a2_4: and_2
		port map(A(3),B(3),quattro1);
	a4: and_4
		port map(uno1,due1,tre1,quattro1,O1);
	b2_1: and_2
		port map(B(0),C(0),uno2);
	b2_2: and_2
		port map(B(1),C(1),due2);
	b2_3: and_2
		port map(B(2),C(2),tre2);
	b2_4: and_2
		port map(B(3),C(3),quattro2);
	b4: and_4
		port map(uno2,due2,tre2,quattro2,O2);
	c2_1: and_2
		port map(C(0),D(0),uno3);
	c2_2: and_2
		port map(C(1),D(1),due3);
	c2_3: and_2
		port map(C(2),C(2),tre3);
	c2_4: and_2
		port map(D(3),D(3),quattro3);
	c4: and_4
		port map(uno3,due3,tre3,quattro3,O3);
end structural;