-- Z:\CAMURATI\ESERCITAZIONE_2
-- VHDL Test Bench created by
-- HDL Bencher 6.1i
-- Fri Mar 16 11:59:53 2007
-- 
-- Notes:
-- 1) This testbench has been automatically generated from
--   your Test Bench Waveform
-- 2) To use this as a user modifiable testbench do the following:
--   - Save it as a file with a .vhd extension (i.e. File->Save As...)
--   - Add it to your project as a testbench source (i.e. Project->Add Source...)
-- 

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_TEXTIO.ALL;
USE STD.TEXTIO.ALL;

ENTITY tester IS
END tester;

ARCHITECTURE testbench_arch OF tester IS
-- If you get a compiler error on the following line,
-- from the menu do Options->Configuration select VHDL 87
FILE RESULTS: TEXT OPEN WRITE_MODE IS "results.txt";
	COMPONENT riconoscitore_1011
		PORT (
			Clear : In  std_logic;
			Clock : In  std_logic;
			Enable : In  std_logic;
			X : In  std_logic;
			CURR_STATE : Out  std_logic_vector (2 DOWNTO 0);
			Y : Out  std_logic
		);
	END COMPONENT;

	SIGNAL Clear : std_logic;
	SIGNAL Clock : std_logic;
	SIGNAL Enable : std_logic;
	SIGNAL X : std_logic;
	SIGNAL CURR_STATE : std_logic_vector (2 DOWNTO 0);
	SIGNAL Y : std_logic;

BEGIN
	UUT : riconoscitore_1011
	PORT MAP (
		Clear => Clear,
		Clock => Clock,
		Enable => Enable,
		X => X,
		CURR_STATE => CURR_STATE,
		Y => Y
	);

	PROCESS -- clock process for Clock,
	BEGIN
		CLOCK_LOOP : LOOP
		Clock <= transport '1';
		WAIT FOR 10 ms;
		Clock <= transport '0';
		WAIT FOR 10 ms;
		WAIT FOR 40 ms;
		Clock <= transport '1';
		WAIT FOR 40 ms;
		END LOOP CLOCK_LOOP;
	END PROCESS;

	PROCESS   -- Process for Clock
		VARIABLE TX_OUT : LINE;
		VARIABLE TX_ERROR : INTEGER := 0;

		PROCEDURE CHECK_Y(
			next_Y : std_logic;
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			-- If compiler error ("/=" is ambiguous) occurs in the next line of code
			-- change compiler settings to use explicit declarations only
			IF (Y /= next_Y) THEN 
				STD.TEXTIO.write(TX_LOC,string'("Error at time="));
				STD.TEXTIO.write(TX_LOC, TX_TIME);
				STD.TEXTIO.write(TX_LOC,string'("ms Y="));
				IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, Y);
				STD.TEXTIO.write(TX_LOC, string'(", Expected = "));
				IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, next_Y);
				STD.TEXTIO.write(TX_LOC, string'(" "));
				TX_STR(TX_LOC.all'range) := TX_LOC.all;
				STD.TEXTIO.writeline(results, TX_LOC);
				STD.TEXTIO.Deallocate(TX_LOC);
				ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
				TX_ERROR := TX_ERROR + 1;
			END IF;
		END;

		PROCEDURE CHECK_CURR_STATE(
			next_CURR_STATE : std_logic_vector (2 DOWNTO 0);
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			-- If compiler error ("/=" is ambiguous) occurs in the next line of code
			-- change compiler settings to use explicit declarations only
			IF (CURR_STATE /= next_CURR_STATE) THEN 
				STD.TEXTIO.write(TX_LOC,string'("Error at time="));
				STD.TEXTIO.write(TX_LOC, TX_TIME);
				STD.TEXTIO.write(TX_LOC,string'("ms CURR_STATE="));
				IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, CURR_STATE);
				STD.TEXTIO.write(TX_LOC, string'(", Expected = "));
				IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, next_CURR_STATE);
				STD.TEXTIO.write(TX_LOC, string'(" "));
				TX_STR(TX_LOC.all'range) := TX_LOC.all;
				STD.TEXTIO.writeline(results, TX_LOC);
				STD.TEXTIO.Deallocate(TX_LOC);
				ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
				TX_ERROR := TX_ERROR + 1;
			END IF;
		END;

		BEGIN
		-- --------------------
		Clear <= transport '1';
		Enable <= transport '0';
		X <= transport '0';
		-- --------------------
		WAIT FOR 20 ms; -- Time=20 ms
		CHECK_Y('0',20);
		-- --------------------
		WAIT FOR 80 ms; -- Time=100 ms
		Clear <= transport '0';
		Enable <= transport '1';
		-- --------------------
		WAIT FOR 20 ms; -- Time=120 ms
		CHECK_Y('0',120);
		-- --------------------
		WAIT FOR 100 ms; -- Time=220 ms
		CHECK_Y('0',220);
		-- --------------------
		WAIT FOR 80 ms; -- Time=300 ms
		Clear <= transport '0';
		X <= transport '1';
		-- --------------------
		WAIT FOR 20 ms; -- Time=320 ms
		CHECK_Y('0',320);
		-- --------------------
		WAIT FOR 80 ms; -- Time=400 ms
		X <= transport '0';
		-- --------------------
		WAIT FOR 20 ms; -- Time=420 ms
		CHECK_Y('0',420);
		-- --------------------
		WAIT FOR 80 ms; -- Time=500 ms
		X <= transport '1';
		-- --------------------
		WAIT FOR 20 ms; -- Time=520 ms
		CHECK_Y('0',520);
		-- --------------------
		WAIT FOR 100 ms; -- Time=620 ms
		CHECK_Y('0',620);
		-- --------------------
		WAIT FOR 80 ms; -- Time=700 ms
		X <= transport '0';
		-- --------------------
		WAIT FOR 20 ms; -- Time=720 ms
		CHECK_Y('0',720);
		-- --------------------
		WAIT FOR 80 ms; -- Time=800 ms
		X <= transport '1';
		-- --------------------
		WAIT FOR 20 ms; -- Time=820 ms
		CHECK_Y('0',820);
		-- --------------------
		WAIT FOR 180 ms; -- Time=1000 ms
		X <= transport '0';
		-- --------------------
		WAIT FOR 100 ms; -- Time=1100 ms
		X <= transport '1';
		-- --------------------
		WAIT FOR 100 ms; -- Time=1200 ms
		X <= transport '0';
		-- --------------------
		WAIT FOR 100 ms; -- Time=1300 ms
		X <= transport '0';
		-- --------------------
		WAIT FOR 100 ms; -- Time=1400 ms
		X <= transport '1';
		-- --------------------
		WAIT FOR 110 ms; -- Time=1510 ms
		-- --------------------

		IF (TX_ERROR = 0) THEN 
			STD.TEXTIO.write(TX_OUT,string'("No errors or warnings"));
			STD.TEXTIO.writeline(results, TX_OUT);
			ASSERT (FALSE) REPORT
				"Simulation successful (not a failure).  No problems detected. "
				SEVERITY FAILURE;
		ELSE
			STD.TEXTIO.write(TX_OUT, TX_ERROR);
			STD.TEXTIO.write(TX_OUT, string'(
				" errors found in simulation"));
			STD.TEXTIO.writeline(results, TX_OUT);
			ASSERT (FALSE) REPORT
				"Errors found during simulation"
				SEVERITY FAILURE;
		END IF;
	END PROCESS;
END testbench_arch;

CONFIGURATION riconoscitore_1011_cfg OF tester IS
	FOR testbench_arch
	END FOR;
END riconoscitore_1011_cfg;