## NOTE: Do not edit this file.
## Auto generated by Project Navigator for VHDL Post-PAR Simulation
##
vlib work
## Compile Post-PAR Model for Module next_state_logic
vcom -87 -explicit  next_state_logic_timesim.vhd
vcom -93 -explicit  test_state.timesim_vhw
vsim -t 1ps -sdfmax /UUT=next_state_logic_timesim.sdf  -lib work test_state
do test_state.udo
view wave
add wave *
view structure
view signals
run -all
## End