-- Z:\CAMURATI\ESERCITAZIONE_2
-- VHDL Test Bench created by
-- HDL Bencher 6.1i
-- Fri Mar 16 11:55:47 2007
-- 
-- Notes:
-- 1) This testbench has been automatically generated from
--   your Test Bench Waveform
-- 2) To use this as a user modifiable testbench do the following:
--   - Save it as a file with a .vhd extension (i.e. File->Save As...)
--   - Add it to your project as a testbench source (i.e. Project->Add Source...)
-- 

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_TEXTIO.ALL;
USE STD.TEXTIO.ALL;

ENTITY test_datapath IS
END test_datapath;

ARCHITECTURE testbench_arch OF test_datapath IS
-- If you get a compiler error on the following line,
-- from the menu do Options->Configuration select VHDL 87
FILE RESULTS: TEXT OPEN WRITE_MODE IS "results.txt";
	COMPONENT datapath
		PORT (
			clk : In  std_logic;
			en : In  std_logic;
			rst : In  std_logic;
			x : In  std_logic;
			y : Out  std_logic;
			current_state : In  std_logic_vector (2 DOWNTO 0);
			next_state : Out  std_logic_vector (2 DOWNTO 0)
		);
	END COMPONENT;

	SIGNAL clk : std_logic;
	SIGNAL en : std_logic;
	SIGNAL rst : std_logic;
	SIGNAL x : std_logic;
	SIGNAL y : std_logic;
	SIGNAL current_state : std_logic_vector (2 DOWNTO 0);
	SIGNAL next_state : std_logic_vector (2 DOWNTO 0);

BEGIN
	UUT : datapath
	PORT MAP (
		clk => clk,
		en => en,
		rst => rst,
		x => x,
		y => y,
		current_state => current_state,
		next_state => next_state
	);

	PROCESS -- clock process for clk,
	BEGIN
		CLOCK_LOOP : LOOP
		clk <= transport '0';
		WAIT FOR 10 ms;
		clk <= transport '1';
		WAIT FOR 10 ms;
		WAIT FOR 40 ms;
		clk <= transport '0';
		WAIT FOR 40 ms;
		END LOOP CLOCK_LOOP;
	END PROCESS;

	PROCESS   -- Process for clk
		VARIABLE TX_OUT : LINE;
		VARIABLE TX_ERROR : INTEGER := 0;

		PROCEDURE CHECK_y(
			next_y : std_logic;
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			-- If compiler error ("/=" is ambiguous) occurs in the next line of code
			-- change compiler settings to use explicit declarations only
			IF (y /= next_y) THEN 
				STD.TEXTIO.write(TX_LOC,string'("Error at time="));
				STD.TEXTIO.write(TX_LOC, TX_TIME);
				STD.TEXTIO.write(TX_LOC,string'("ms y="));
				IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, y);
				STD.TEXTIO.write(TX_LOC, string'(", Expected = "));
				IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, next_y);
				STD.TEXTIO.write(TX_LOC, string'(" "));
				TX_STR(TX_LOC.all'range) := TX_LOC.all;
				STD.TEXTIO.writeline(results, TX_LOC);
				STD.TEXTIO.Deallocate(TX_LOC);
				ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
				TX_ERROR := TX_ERROR + 1;
			END IF;
		END;

		PROCEDURE CHECK_next_state(
			next_next_state : std_logic_vector (2 DOWNTO 0);
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			-- If compiler error ("/=" is ambiguous) occurs in the next line of code
			-- change compiler settings to use explicit declarations only
			IF (next_state /= next_next_state) THEN 
				STD.TEXTIO.write(TX_LOC,string'("Error at time="));
				STD.TEXTIO.write(TX_LOC, TX_TIME);
				STD.TEXTIO.write(TX_LOC,string'("ms next_state="));
				IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, next_state);
				STD.TEXTIO.write(TX_LOC, string'(", Expected = "));
				IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, next_next_state);
				STD.TEXTIO.write(TX_LOC, string'(" "));
				TX_STR(TX_LOC.all'range) := TX_LOC.all;
				STD.TEXTIO.writeline(results, TX_LOC);
				STD.TEXTIO.Deallocate(TX_LOC);
				ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
				TX_ERROR := TX_ERROR + 1;
			END IF;
		END;

		BEGIN
		-- --------------------
		en <= transport '0';
		rst <= transport '1';
		x <= transport '0';
		current_state <= transport std_logic_vector'("000"); --0
		-- --------------------
		WAIT FOR 100 ms; -- Time=100 ms
		en <= transport '1';
		rst <= transport '0';
		x <= transport '1';
		current_state <= transport std_logic_vector'("000"); --0
		-- --------------------
		WAIT FOR 100 ms; -- Time=200 ms
		x <= transport '0';
		current_state <= transport std_logic_vector'("001"); --1
		-- --------------------
		WAIT FOR 100 ms; -- Time=300 ms
		x <= transport '1';
		current_state <= transport std_logic_vector'("011"); --3
		-- --------------------
		WAIT FOR 100 ms; -- Time=400 ms
		current_state <= transport std_logic_vector'("010"); --2
		-- --------------------
		WAIT FOR 100 ms; -- Time=500 ms
		x <= transport '0';
		current_state <= transport std_logic_vector'("110"); --6
		-- --------------------
		WAIT FOR 300 ms; -- Time=800 ms
		x <= transport '0';
		-- --------------------
		WAIT FOR 210 ms; -- Time=1010 ms
		-- --------------------

		IF (TX_ERROR = 0) THEN 
			STD.TEXTIO.write(TX_OUT,string'("No errors or warnings"));
			STD.TEXTIO.writeline(results, TX_OUT);
			ASSERT (FALSE) REPORT
				"Simulation successful (not a failure).  No problems detected. "
				SEVERITY FAILURE;
		ELSE
			STD.TEXTIO.write(TX_OUT, TX_ERROR);
			STD.TEXTIO.write(TX_OUT, string'(
				" errors found in simulation"));
			STD.TEXTIO.writeline(results, TX_OUT);
			ASSERT (FALSE) REPORT
				"Errors found during simulation"
				SEVERITY FAILURE;
		END IF;
	END PROCESS;
END testbench_arch;

CONFIGURATION datapath_cfg OF test_datapath IS
	FOR testbench_arch
	END FOR;
END datapath_cfg;