-- Xilinx Vhdl netlist produced by netgen application (version G.35)
-- Command       : -intstyle ise -s 4 -pcf riconoscitore_1011.pcf -ngm riconoscitore_1011.ngm -rpw 100 -tpw 0 -ar Structure -xon true -w -ofmt vhdl -sim riconoscitore_1011.ncd riconoscitore_1011_timesim.vhd 
-- Input file    : riconoscitore_1011.ncd
-- Output file   : riconoscitore_1011_timesim.vhd
-- Design name   : riconoscitore_1011
-- # of Entities : 1
-- Xilinx        : C:/Program Files/Xilinx
-- Device        : 3s200ft256-4 (PRODUCTION 1.32 2004-06-25)

-- This vhdl netlist is a simulation model and uses simulation 
-- primitives which may not represent the true implementation of the 
-- device, however the netlist is functionally correct and should not 
-- be modified. This file cannot be synthesized and should only be used 
-- with supported simulation tools.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library SIMPRIM;
use SIMPRIM.VCOMPONENTS.ALL;
use SIMPRIM.VPACKAGE.ALL;

entity riconoscitore_1011 is
  port (
    Y : out STD_LOGIC; 
    Enable : in STD_LOGIC := 'X'; 
    Clock : in STD_LOGIC := 'X'; 
    X : in STD_LOGIC := 'X'; 
    Clear : in STD_LOGIC := 'X'; 
    CURR_STATE : out STD_LOGIC_VECTOR ( 2 downto 0 ) 
  );
end riconoscitore_1011;

architecture Structure of riconoscitore_1011 is
  signal Clear_IBUF : STD_LOGIC; 
  signal Clock_BUFGP : STD_LOGIC; 
  signal Clock_BUFGP_IBUFG : STD_LOGIC; 
  signal X_IBUF : STD_LOGIC; 
  signal XLXI_3_y : STD_LOGIC; 
  signal Enable_BUFGP_IBUFG : STD_LOGIC; 
  signal GLOBAL_LOGIC1 : STD_LOGIC; 
  signal Enable_BUFGP : STD_LOGIC; 
  signal N1745 : STD_LOGIC; 
  signal CHOICE158 : STD_LOGIC; 
  signal N1743 : STD_LOGIC; 
  signal CHOICE182 : STD_LOGIC; 
  signal CHOICE164 : STD_LOGIC; 
  signal GLOBAL_LOGIC1_0 : STD_LOGIC; 
  signal GSR : STD_LOGIC; 
  signal GTS : STD_LOGIC; 
  signal Clear_INBUF : STD_LOGIC; 
  signal CURR_STATE_0_ENABLE : STD_LOGIC; 
  signal CURR_STATE_0_GTS_OR_T : STD_LOGIC; 
  signal CURR_STATE_0_O : STD_LOGIC; 
  signal CURR_STATE_1_OUTPUT_OTCLK1INV : STD_LOGIC; 
  signal CURR_STATE_1_ENABLE : STD_LOGIC; 
  signal CURR_STATE_1_GTS_OR_T : STD_LOGIC; 
  signal CURR_STATE_1_O : STD_LOGIC; 
  signal CURR_STATE_2_ENABLE : STD_LOGIC; 
  signal CURR_STATE_2_GTS_OR_T : STD_LOGIC; 
  signal CURR_STATE_2_O : STD_LOGIC; 
  signal CURR_STATE_0_OUTPUT_OTCLK1INV : STD_LOGIC; 
  signal Clock_INBUF : STD_LOGIC; 
  signal X_INBUF : STD_LOGIC; 
  signal XLXI_4_nstate_0_1 : STD_LOGIC; 
  signal CURR_STATE_0_OUTPUT_OFF_OSR_USED : STD_LOGIC; 
  signal CURR_STATE_0_OUTPUT_OFF_O1INV : STD_LOGIC; 
  signal Y_ENABLE : STD_LOGIC; 
  signal Y_GTS_OR_T : STD_LOGIC; 
  signal Y_O : STD_LOGIC; 
  signal Enable_INBUF : STD_LOGIC; 
  signal Enable_BUFGP_BUFG_S_INVNOT : STD_LOGIC; 
  signal Clock_BUFGP_BUFG_S_INVNOT : STD_LOGIC; 
  signal XLXI_3_y_F : STD_LOGIC; 
  signal XLXI_3_y_DYMUX : STD_LOGIC; 
  signal XLXI_3_n00081_O : STD_LOGIC; 
  signal XLXI_3_y_CLKINVNOT : STD_LOGIC; 
  signal XLXI_4_nstate_2_DYMUX : STD_LOGIC; 
  signal XLXI_4_nstate_2_SRINV : STD_LOGIC; 
  signal XLXI_4_nstate_2_CLKINV : STD_LOGIC; 
  signal CHOICE158_F : STD_LOGIC; 
  signal XLXI_3_n0007_1_DXMUX : STD_LOGIC; 
  signal XLXI_3_n0009_1_71_O : STD_LOGIC; 
  signal XLXI_3_n0007_1_G : STD_LOGIC; 
  signal XLXI_3_n0007_1_CLKINVNOT : STD_LOGIC; 
  signal XLXI_3_n0007_0_DXMUX : STD_LOGIC; 
  signal XLXI_3_n0009_0_64_O : STD_LOGIC; 
  signal XLXI_3_n0007_0_G : STD_LOGIC; 
  signal XLXI_3_n0007_0_CLKINVNOT : STD_LOGIC; 
  signal XLXI_3_n0007_2_DXMUX : STD_LOGIC; 
  signal XLXI_3_n0009_2_52_O : STD_LOGIC; 
  signal XLXI_3_n0007_2_G : STD_LOGIC; 
  signal XLXI_3_n0007_2_CLKINVNOT : STD_LOGIC; 
  signal XLXI_4_nstate_1_DXMUX : STD_LOGIC; 
  signal XLXI_4_nstate_1_DYMUX : STD_LOGIC; 
  signal XLXI_4_nstate_1_SRINV : STD_LOGIC; 
  signal XLXI_4_nstate_1_CLKINV : STD_LOGIC; 
  signal XLXI_3_y_FFY_RST : STD_LOGIC; 
  signal XLXI_3_n0007_1_FFX_RST : STD_LOGIC; 
  signal XLXI_4_nstate_1_1 : STD_LOGIC; 
  signal CURR_STATE_1_OUTPUT_OFF_OSR_USED : STD_LOGIC; 
  signal CURR_STATE_1_OUTPUT_OFF_O1INV : STD_LOGIC; 
  signal CURR_STATE_2_OUTPUT_OTCLK1INV : STD_LOGIC; 
  signal XLXI_4_nstate_2_1 : STD_LOGIC; 
  signal CURR_STATE_2_OUTPUT_OFF_OSR_USED : STD_LOGIC; 
  signal CURR_STATE_2_OUTPUT_OFF_O1INV : STD_LOGIC; 
  signal XLXI_3_n0007_0_FFX_RST : STD_LOGIC; 
  signal XLXI_3_n0007_2_FFX_RST : STD_LOGIC; 
  signal VCC : STD_LOGIC; 
  signal GND : STD_LOGIC; 
  signal NlwInverterSignal_XLXI_3_y_CLK : STD_LOGIC; 
  signal NlwInverterSignal_XLXI_3_n0007_1_CLK : STD_LOGIC; 
  signal NlwInverterSignal_XLXI_3_n0007_0_CLK : STD_LOGIC; 
  signal NlwInverterSignal_XLXI_3_n0007_2_CLK : STD_LOGIC; 
  signal XLXI_3_n0007 : STD_LOGIC_VECTOR ( 2 downto 0 ); 
  signal XLXI_4_nstate : STD_LOGIC_VECTOR ( 2 downto 0 ); 
begin
  Clear_IBUF_0 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => Clear,
      O => Clear_INBUF
    );
  CURR_STATE_0_OBUF : X_TRI_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => CURR_STATE_0_O,
      CTL => CURR_STATE_0_ENABLE,
      O => CURR_STATE(0)
    );
  CURR_STATE_0_ENABLEINV : X_INV
    port map (
      I => CURR_STATE_0_GTS_OR_T,
      O => CURR_STATE_0_ENABLE
    );
  CURR_STATE_0_GTS_OR_T_1 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => GTS,
      O => CURR_STATE_0_GTS_OR_T
    );
  CURR_STATE_1_OUTPUT_OTCLK1INV_2 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => Clock_BUFGP,
      O => CURR_STATE_1_OUTPUT_OTCLK1INV
    );
  CURR_STATE_1_OBUF : X_TRI_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => CURR_STATE_1_O,
      CTL => CURR_STATE_1_ENABLE,
      O => CURR_STATE(1)
    );
  CURR_STATE_1_ENABLEINV : X_INV
    port map (
      I => CURR_STATE_1_GTS_OR_T,
      O => CURR_STATE_1_ENABLE
    );
  CURR_STATE_1_GTS_OR_T_3 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => GTS,
      O => CURR_STATE_1_GTS_OR_T
    );
  CURR_STATE_2_OBUF : X_TRI_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => CURR_STATE_2_O,
      CTL => CURR_STATE_2_ENABLE,
      O => CURR_STATE(2)
    );
  CURR_STATE_2_ENABLEINV : X_INV
    port map (
      I => CURR_STATE_2_GTS_OR_T,
      O => CURR_STATE_2_ENABLE
    );
  CURR_STATE_2_GTS_OR_T_4 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => GTS,
      O => CURR_STATE_2_GTS_OR_T
    );
  CURR_STATE_0_OUTPUT_OTCLK1INV_5 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => Clock_BUFGP,
      O => CURR_STATE_0_OUTPUT_OTCLK1INV
    );
  Clock_BUFGP_IBUFG_6 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => Clock,
      O => Clock_INBUF
    );
  X_IBUF_7 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => X,
      O => X_INBUF
    );
  CURR_STATE_0_OUTPUT_OFF_OMUX : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => XLXI_4_nstate_0_1,
      O => CURR_STATE_0_O
    );
  CURR_STATE_0_OUTPUT_OFF_OSR_USED_8 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => Clear_IBUF,
      O => CURR_STATE_0_OUTPUT_OFF_OSR_USED
    );
  CURR_STATE_0_OUTPUT_OFF_O1INV_9 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => XLXI_3_n0007(0),
      O => CURR_STATE_0_OUTPUT_OFF_O1INV
    );
  Y_OBUF : X_TRI_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => Y_O,
      CTL => Y_ENABLE,
      O => Y
    );
  Y_ENABLEINV : X_INV
    port map (
      I => Y_GTS_OR_T,
      O => Y_ENABLE
    );
  Y_GTS_OR_T_10 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => GTS,
      O => Y_GTS_OR_T
    );
  Enable_BUFGP_IBUFG_11 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => Enable,
      O => Enable_INBUF
    );
  XLXI_4_nstate_0_1_12 : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => CURR_STATE_0_OUTPUT_OFF_O1INV,
      CE => VCC,
      CLK => CURR_STATE_0_OUTPUT_OTCLK1INV,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => CURR_STATE_0_OUTPUT_OFF_OSR_USED,
      O => XLXI_4_nstate_0_1
    );
  Enable_BUFGP_BUFG : X_BUFGMUX
    port map (
      I0 => Enable_BUFGP_IBUFG,
      I1 => GND,
      S => Enable_BUFGP_BUFG_S_INVNOT,
      O => Enable_BUFGP,
      GSR => GSR
    );
  Enable_BUFGP_BUFG_SINV : X_INV
    port map (
      I => GLOBAL_LOGIC1_0,
      O => Enable_BUFGP_BUFG_S_INVNOT
    );
  Clock_BUFGP_BUFG : X_BUFGMUX
    port map (
      I0 => Clock_BUFGP_IBUFG,
      I1 => GND,
      S => Clock_BUFGP_BUFG_S_INVNOT,
      O => Clock_BUFGP,
      GSR => GSR
    );
  Clock_BUFGP_BUFG_SINV : X_INV
    port map (
      I => GLOBAL_LOGIC1,
      O => Clock_BUFGP_BUFG_S_INVNOT
    );
  XLXI_3_y_XUSED : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => XLXI_3_y_F,
      O => N1745
    );
  XLXI_3_y_DYMUX_13 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => XLXI_3_n00081_O,
      O => XLXI_3_y_DYMUX
    );
  XLXI_3_y_CLKINV : X_INV
    port map (
      I => Enable_BUFGP,
      O => XLXI_3_y_CLKINVNOT
    );
  XLXI_4_nstate_2_DYMUX_14 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => XLXI_3_n0007(2),
      O => XLXI_4_nstate_2_DYMUX
    );
  XLXI_4_nstate_2_SRINV_15 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => Clear_IBUF,
      O => XLXI_4_nstate_2_SRINV
    );
  XLXI_4_nstate_2_CLKINV_16 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => Clock_BUFGP,
      O => XLXI_4_nstate_2_CLKINV
    );
  CHOICE158_XUSED : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => CHOICE158_F,
      O => CHOICE158
    );
  XLXI_3_n0007_1_DXMUX_17 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => XLXI_3_n0009_1_71_O,
      O => XLXI_3_n0007_1_DXMUX
    );
  XLXI_3_n0007_1_YUSED : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => XLXI_3_n0007_1_G,
      O => N1743
    );
  XLXI_3_n0007_1_CLKINV : X_INV
    port map (
      I => Enable_BUFGP,
      O => XLXI_3_n0007_1_CLKINVNOT
    );
  XLXI_3_n0007_0_DXMUX_18 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => XLXI_3_n0009_0_64_O,
      O => XLXI_3_n0007_0_DXMUX
    );
  XLXI_3_n0007_0_YUSED : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => XLXI_3_n0007_0_G,
      O => CHOICE182
    );
  XLXI_3_n0007_0_CLKINV : X_INV
    port map (
      I => Enable_BUFGP,
      O => XLXI_3_n0007_0_CLKINVNOT
    );
  XLXI_3_n0007_2_DXMUX_19 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => XLXI_3_n0009_2_52_O,
      O => XLXI_3_n0007_2_DXMUX
    );
  XLXI_3_n0007_2_YUSED : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => XLXI_3_n0007_2_G,
      O => CHOICE164
    );
  XLXI_3_n0007_2_CLKINV : X_INV
    port map (
      I => Enable_BUFGP,
      O => XLXI_3_n0007_2_CLKINVNOT
    );
  XLXI_4_nstate_1_DXMUX_20 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => XLXI_3_n0007(1),
      O => XLXI_4_nstate_1_DXMUX
    );
  XLXI_4_nstate_1_DYMUX_21 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => XLXI_3_n0007(0),
      O => XLXI_4_nstate_1_DYMUX
    );
  XLXI_4_nstate_1_SRINV_22 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => Clear_IBUF,
      O => XLXI_4_nstate_1_SRINV
    );
  XLXI_4_nstate_1_CLKINV_23 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => Clock_BUFGP,
      O => XLXI_4_nstate_1_CLKINV
    );
  XLXI_3_n00081 : X_LUT4
    generic map(
      INIT => X"A2A0"
    )
    port map (
      ADR0 => XLXI_4_nstate(2),
      ADR1 => XLXI_4_nstate(0),
      ADR2 => XLXI_3_y,
      ADR3 => XLXI_4_nstate(1),
      O => XLXI_3_n00081_O
    );
  XLXI_3_y_24 : X_LATCHE
    generic map(
      INIT => '0'
    )
    port map (
      I => XLXI_3_y_DYMUX,
      GE => VCC,
      CLK => NlwInverterSignal_XLXI_3_y_CLK,
      SET => GND,
      RST => XLXI_3_y_FFY_RST,
      O => XLXI_3_y
    );
  XLXI_3_y_FFY_RSTOR : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => GSR,
      O => XLXI_3_y_FFY_RST
    );
  XLXI_3_n0009_1_71_SW3 : X_LUT4
    generic map(
      INIT => X"F6BF"
    )
    port map (
      ADR0 => XLXI_4_nstate(2),
      ADR1 => XLXI_4_nstate(1),
      ADR2 => XLXI_4_nstate(0),
      ADR3 => X_IBUF,
      O => XLXI_3_y_F
    );
  XLXI_4_nstate_2 : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => XLXI_4_nstate_2_DYMUX,
      CE => VCC,
      CLK => XLXI_4_nstate_2_CLKINV,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => XLXI_4_nstate_2_SRINV,
      O => XLXI_4_nstate(2)
    );
  XLXI_3_n0009_2_29 : X_LUT4
    generic map(
      INIT => X"B2B1"
    )
    port map (
      ADR0 => XLXI_4_nstate(0),
      ADR1 => XLXI_4_nstate(1),
      ADR2 => XLXI_4_nstate(2),
      ADR3 => X_IBUF,
      O => CHOICE158_F
    );
  XLXI_3_n0009_1_71_SW2 : X_LUT4
    generic map(
      INIT => X"0A26"
    )
    port map (
      ADR0 => XLXI_4_nstate(1),
      ADR1 => XLXI_4_nstate(0),
      ADR2 => XLXI_4_nstate(2),
      ADR3 => X_IBUF,
      O => XLXI_3_n0007_1_G
    );
  XLXI_3_n0009_0_56 : X_LUT4
    generic map(
      INIT => X"4146"
    )
    port map (
      ADR0 => XLXI_4_nstate(0),
      ADR1 => XLXI_4_nstate(1),
      ADR2 => XLXI_4_nstate(2),
      ADR3 => X_IBUF,
      O => XLXI_3_n0007_0_G
    );
  XLXI_3_n0009_1_71 : X_LUT4
    generic map(
      INIT => X"AAF0"
    )
    port map (
      ADR0 => N1745,
      ADR1 => VCC,
      ADR2 => N1743,
      ADR3 => XLXI_3_n0007(1),
      O => XLXI_3_n0009_1_71_O
    );
  XLXI_3_n0007_1 : X_LATCHE
    generic map(
      INIT => '0'
    )
    port map (
      I => XLXI_3_n0007_1_DXMUX,
      GE => VCC,
      CLK => NlwInverterSignal_XLXI_3_n0007_1_CLK,
      SET => GND,
      RST => XLXI_3_n0007_1_FFX_RST,
      O => XLXI_3_n0007(1)
    );
  XLXI_3_n0007_1_FFX_RSTOR : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => GSR,
      O => XLXI_3_n0007_1_FFX_RST
    );
  CURR_STATE_1_OUTPUT_OFF_OMUX : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => XLXI_4_nstate_1_1,
      O => CURR_STATE_1_O
    );
  CURR_STATE_1_OUTPUT_OFF_OSR_USED_25 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => Clear_IBUF,
      O => CURR_STATE_1_OUTPUT_OFF_OSR_USED
    );
  CURR_STATE_1_OUTPUT_OFF_O1INV_26 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => XLXI_3_n0007(1),
      O => CURR_STATE_1_OUTPUT_OFF_O1INV
    );
  XLXI_4_nstate_1_1_27 : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => CURR_STATE_1_OUTPUT_OFF_O1INV,
      CE => VCC,
      CLK => CURR_STATE_1_OUTPUT_OTCLK1INV,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => CURR_STATE_1_OUTPUT_OFF_OSR_USED,
      O => XLXI_4_nstate_1_1
    );
  CURR_STATE_2_OUTPUT_OTCLK1INV_28 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => Clock_BUFGP,
      O => CURR_STATE_2_OUTPUT_OTCLK1INV
    );
  CURR_STATE_2_OUTPUT_OFF_OMUX : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => XLXI_4_nstate_2_1,
      O => CURR_STATE_2_O
    );
  CURR_STATE_2_OUTPUT_OFF_OSR_USED_29 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => Clear_IBUF,
      O => CURR_STATE_2_OUTPUT_OFF_OSR_USED
    );
  CURR_STATE_2_OUTPUT_OFF_O1INV_30 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => XLXI_3_n0007(2),
      O => CURR_STATE_2_OUTPUT_OFF_O1INV
    );
  XLXI_4_nstate_2_1_31 : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => CURR_STATE_2_OUTPUT_OFF_O1INV,
      CE => VCC,
      CLK => CURR_STATE_2_OUTPUT_OTCLK1INV,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => CURR_STATE_2_OUTPUT_OFF_OSR_USED,
      O => XLXI_4_nstate_2_1
    );
  XLXI_3_n0009_0_64 : X_LUT4
    generic map(
      INIT => X"FFB0"
    )
    port map (
      ADR0 => XLXI_4_nstate(2),
      ADR1 => XLXI_4_nstate(1),
      ADR2 => XLXI_3_n0007(0),
      ADR3 => CHOICE182,
      O => XLXI_3_n0009_0_64_O
    );
  XLXI_3_n0007_0 : X_LATCHE
    generic map(
      INIT => '0'
    )
    port map (
      I => XLXI_3_n0007_0_DXMUX,
      GE => VCC,
      CLK => NlwInverterSignal_XLXI_3_n0007_0_CLK,
      SET => GND,
      RST => XLXI_3_n0007_0_FFX_RST,
      O => XLXI_3_n0007(0)
    );
  XLXI_3_n0007_0_FFX_RSTOR : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => GSR,
      O => XLXI_3_n0007_0_FFX_RST
    );
  XLXI_3_n0009_2_50 : X_LUT4
    generic map(
      INIT => X"0020"
    )
    port map (
      ADR0 => X_IBUF,
      ADR1 => XLXI_4_nstate(2),
      ADR2 => XLXI_4_nstate(1),
      ADR3 => XLXI_4_nstate(0),
      O => XLXI_3_n0007_2_G
    );
  XLXI_3_n0009_2_52 : X_LUT4
    generic map(
      INIT => X"F8F8"
    )
    port map (
      ADR0 => XLXI_3_n0007(2),
      ADR1 => CHOICE158,
      ADR2 => CHOICE164,
      ADR3 => VCC,
      O => XLXI_3_n0009_2_52_O
    );
  XLXI_3_n0007_2 : X_LATCHE
    generic map(
      INIT => '0'
    )
    port map (
      I => XLXI_3_n0007_2_DXMUX,
      GE => VCC,
      CLK => NlwInverterSignal_XLXI_3_n0007_2_CLK,
      SET => GND,
      RST => XLXI_3_n0007_2_FFX_RST,
      O => XLXI_3_n0007(2)
    );
  XLXI_3_n0007_2_FFX_RSTOR : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => GSR,
      O => XLXI_3_n0007_2_FFX_RST
    );
  XLXI_4_nstate_0 : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => XLXI_4_nstate_1_DYMUX,
      CE => VCC,
      CLK => XLXI_4_nstate_1_CLKINV,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => XLXI_4_nstate_1_SRINV,
      O => XLXI_4_nstate(0)
    );
  XLXI_4_nstate_1 : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => XLXI_4_nstate_1_DXMUX,
      CE => VCC,
      CLK => XLXI_4_nstate_1_CLKINV,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => XLXI_4_nstate_1_SRINV,
      O => XLXI_4_nstate(1)
    );
  PWR_VCC_0_LOGICAL_ONE : X_ONE
    port map (
      O => GLOBAL_LOGIC1
    );
  PWR_VCC_1_LOGICAL_ONE : X_ONE
    port map (
      O => GLOBAL_LOGIC1_0
    );
  Clear_IFF_IMUX : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => Clear_INBUF,
      O => Clear_IBUF
    );
  Clock_IFF_IMUX : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => Clock_INBUF,
      O => Clock_BUFGP_IBUFG
    );
  X_IFF_IMUX : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => X_INBUF,
      O => X_IBUF
    );
  Y_OUTPUT_OFF_OMUX : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => XLXI_3_y,
      O => Y_O
    );
  Enable_IFF_IMUX : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => Enable_INBUF,
      O => Enable_BUFGP_IBUFG
    );
  NlwBlock_riconoscitore_1011_VCC : X_ONE
    port map (
      O => VCC
    );
  NlwBlock_riconoscitore_1011_GND : X_ZERO
    port map (
      O => GND
    );
  NlwInverterBlock_XLXI_3_y_CLK : X_INV
    port map (
      I => XLXI_3_y_CLKINVNOT,
      O => NlwInverterSignal_XLXI_3_y_CLK
    );
  NlwInverterBlock_XLXI_3_n0007_1_CLK : X_INV
    port map (
      I => XLXI_3_n0007_1_CLKINVNOT,
      O => NlwInverterSignal_XLXI_3_n0007_1_CLK
    );
  NlwInverterBlock_XLXI_3_n0007_0_CLK : X_INV
    port map (
      I => XLXI_3_n0007_0_CLKINVNOT,
      O => NlwInverterSignal_XLXI_3_n0007_0_CLK
    );
  NlwInverterBlock_XLXI_3_n0007_2_CLK : X_INV
    port map (
      I => XLXI_3_n0007_2_CLKINVNOT,
      O => NlwInverterSignal_XLXI_3_n0007_2_CLK
    );
  NlwBlockROC : X_ROC
    generic map (ROC_WIDTH => 100 ns)
    port map (O => GSR);
  NlwBlockTOC : X_TOC
    port map (O => GTS);

end Structure;