-- Xilinx Vhdl netlist produced by netgen application (version G.35)
-- Command       : -intstyle ise -s 4 -pcf next_state_logic.pcf -ngm next_state_logic.ngm -rpw 100 -tpw 0 -ar Structure -xon true -w -ofmt vhdl -sim next_state_logic.ncd next_state_logic_timesim.vhd 
-- Input file    : next_state_logic.ncd
-- Output file   : next_state_logic_timesim.vhd
-- Design name   : next_state_logic
-- # of Entities : 1
-- Xilinx        : C:/Program Files/Xilinx
-- Device        : 3s200ft256-4 (PRODUCTION 1.32 2004-06-25)

-- This vhdl netlist is a simulation model and uses simulation 
-- primitives which may not represent the true implementation of the 
-- device, however the netlist is functionally correct and should not 
-- be modified. This file cannot be synthesized and should only be used 
-- with supported simulation tools.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library SIMPRIM;
use SIMPRIM.VCOMPONENTS.ALL;
use SIMPRIM.VPACKAGE.ALL;

entity next_state_logic is
  port (
    clr : in STD_LOGIC := 'X'; 
    clk : in STD_LOGIC := 'X'; 
    state_out : out STD_LOGIC_VECTOR ( 2 downto 0 ); 
    state_in : in STD_LOGIC_VECTOR ( 2 downto 0 ) 
  );
end next_state_logic;

architecture Structure of next_state_logic is
  signal clk_BUFGP_IBUFG : STD_LOGIC; 
  signal clr_IBUF : STD_LOGIC; 
  signal clk_BUFGP : STD_LOGIC; 
  signal GLOBAL_LOGIC1 : STD_LOGIC; 
  signal GSR : STD_LOGIC; 
  signal GTS : STD_LOGIC; 
  signal clk_INBUF : STD_LOGIC; 
  signal clr_INBUF : STD_LOGIC; 
  signal state_in_0_INBUF : STD_LOGIC; 
  signal state_in_1_INBUF : STD_LOGIC; 
  signal state_in_2_IFF_IFFDMUX : STD_LOGIC; 
  signal state_in_2_IFF_ICLK1INV : STD_LOGIC; 
  signal state_in_2_IFF_ISR_USED : STD_LOGIC; 
  signal state_in_2_INBUF : STD_LOGIC; 
  signal state_out_0_ENABLE : STD_LOGIC; 
  signal state_out_0_GTS_OR_T : STD_LOGIC; 
  signal state_out_0_O : STD_LOGIC; 
  signal state_out_1_ENABLE : STD_LOGIC; 
  signal state_out_1_GTS_OR_T : STD_LOGIC; 
  signal state_out_1_O : STD_LOGIC; 
  signal state_out_2_ENABLE : STD_LOGIC; 
  signal state_out_2_GTS_OR_T : STD_LOGIC; 
  signal state_out_2_O : STD_LOGIC; 
  signal clk_BUFGP_BUFG_S_INVNOT : STD_LOGIC; 
  signal state_in_1_IFF_ISR_USED : STD_LOGIC; 
  signal state_in_1_IFF_ICLK1INV : STD_LOGIC; 
  signal state_in_1_IFF_IFFDMUX : STD_LOGIC; 
  signal state_in_0_IFF_ISR_USED : STD_LOGIC; 
  signal state_in_0_IFF_ICLK1INV : STD_LOGIC; 
  signal state_in_0_IFF_IFFDMUX : STD_LOGIC; 
  signal GND : STD_LOGIC; 
  signal VCC : STD_LOGIC; 
  signal nstate : STD_LOGIC_VECTOR ( 2 downto 0 ); 
begin
  clk_BUFGP_IBUFG_0 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => clk,
      O => clk_INBUF
    );
  clr_IBUF_1 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => clr,
      O => clr_INBUF
    );
  state_in_0_IBUF : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => state_in(0),
      O => state_in_0_INBUF
    );
  state_in_1_IBUF : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => state_in(1),
      O => state_in_1_INBUF
    );
  state_in_2_IFF_ICLK1INV_2 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => clk_BUFGP,
      O => state_in_2_IFF_ICLK1INV
    );
  state_in_2_IFF_ISR_USED_3 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => clr_IBUF,
      O => state_in_2_IFF_ISR_USED
    );
  state_in_2_IFF_IFFDMUX_4 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => state_in_2_INBUF,
      O => state_in_2_IFF_IFFDMUX
    );
  state_in_2_IBUF : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => state_in(2),
      O => state_in_2_INBUF
    );
  state_out_0_OBUF : X_TRI_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => state_out_0_O,
      CTL => state_out_0_ENABLE,
      O => state_out(0)
    );
  state_out_0_ENABLEINV : X_INV
    port map (
      I => state_out_0_GTS_OR_T,
      O => state_out_0_ENABLE
    );
  state_out_0_GTS_OR_T_5 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => GTS,
      O => state_out_0_GTS_OR_T
    );
  state_out_1_OBUF : X_TRI_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => state_out_1_O,
      CTL => state_out_1_ENABLE,
      O => state_out(1)
    );
  state_out_1_ENABLEINV : X_INV
    port map (
      I => state_out_1_GTS_OR_T,
      O => state_out_1_ENABLE
    );
  state_out_1_GTS_OR_T_6 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => GTS,
      O => state_out_1_GTS_OR_T
    );
  state_out_2_OBUF : X_TRI_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => state_out_2_O,
      CTL => state_out_2_ENABLE,
      O => state_out(2)
    );
  state_out_2_ENABLEINV : X_INV
    port map (
      I => state_out_2_GTS_OR_T,
      O => state_out_2_ENABLE
    );
  state_out_2_GTS_OR_T_7 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => GTS,
      O => state_out_2_GTS_OR_T
    );
  clk_BUFGP_BUFG : X_BUFGMUX
    port map (
      I0 => clk_BUFGP_IBUFG,
      I1 => GND,
      S => clk_BUFGP_BUFG_S_INVNOT,
      O => clk_BUFGP,
      GSR => GSR
    );
  clk_BUFGP_BUFG_SINV : X_INV
    port map (
      I => GLOBAL_LOGIC1,
      O => clk_BUFGP_BUFG_S_INVNOT
    );
  state_in_1_IFF_IFFDMUX_8 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => state_in_1_INBUF,
      O => state_in_1_IFF_IFFDMUX
    );
  state_in_1_IFF_ISR_USED_9 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => clr_IBUF,
      O => state_in_1_IFF_ISR_USED
    );
  state_in_1_IFF_ICLK1INV_10 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => clk_BUFGP,
      O => state_in_1_IFF_ICLK1INV
    );
  state_in_0_IFF_IFFDMUX_11 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => state_in_0_INBUF,
      O => state_in_0_IFF_IFFDMUX
    );
  state_in_0_IFF_ISR_USED_12 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => clr_IBUF,
      O => state_in_0_IFF_ISR_USED
    );
  state_in_0_IFF_ICLK1INV_13 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => clk_BUFGP,
      O => state_in_0_IFF_ICLK1INV
    );
  nstate_0 : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => state_in_0_IFF_IFFDMUX,
      CE => VCC,
      CLK => state_in_0_IFF_ICLK1INV,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => state_in_0_IFF_ISR_USED,
      O => nstate(0)
    );
  nstate_1 : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => state_in_1_IFF_IFFDMUX,
      CE => VCC,
      CLK => state_in_1_IFF_ICLK1INV,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => state_in_1_IFF_ISR_USED,
      O => nstate(1)
    );
  nstate_2 : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => state_in_2_IFF_IFFDMUX,
      CE => VCC,
      CLK => state_in_2_IFF_ICLK1INV,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => state_in_2_IFF_ISR_USED,
      O => nstate(2)
    );
  PWR_VCC_0_LOGICAL_ONE : X_ONE
    port map (
      O => GLOBAL_LOGIC1
    );
  clk_IFF_IMUX : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => clk_INBUF,
      O => clk_BUFGP_IBUFG
    );
  clr_IFF_IMUX : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => clr_INBUF,
      O => clr_IBUF
    );
  state_out_0_OUTPUT_OFF_OMUX : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => nstate(0),
      O => state_out_0_O
    );
  state_out_1_OUTPUT_OFF_OMUX : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => nstate(1),
      O => state_out_1_O
    );
  state_out_2_OUTPUT_OFF_OMUX : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => nstate(2),
      O => state_out_2_O
    );
  NlwBlock_next_state_logic_GND : X_ZERO
    port map (
      O => GND
    );
  NlwBlock_next_state_logic_VCC : X_ONE
    port map (
      O => VCC
    );
  NlwBlockROC : X_ROC
    generic map (ROC_WIDTH => 100 ns)
    port map (O => GSR);
  NlwBlockTOC : X_TOC
    port map (O => GTS);

end Structure;