library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity next_state_logic is
Port(clk,clr:in std_logic;
	state_in:in std_logic_vector(2 downto 0);
	state_out:out std_logic_vector(2 downto 0));
end next_state_logic;

architecture Behavioral of next_state_logic is



begin

process(clk)
variable nstate:std_logic_vector(2 downto 0):="000";
begin
if clk'event and clk='1' then
	if clr='1' then
		nstate:="000";
	else
		nstate:=state_in;
	end if;
end if;
state_out<=nstate;
end process;

end Behavioral;