Release 6.3i Par G.35
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.

LABINF34::  Fri Mar 16 11:52:21 2007


C:/Program Files/Xilinx/bin/nt/par.exe -w -intstyle ise -ol std -t 1
next_state_logic_map.ncd next_state_logic.ncd next_state_logic.pcf 


Constraints file: next_state_logic.pcf

Loading device database for application Par from file
"next_state_logic_map.ncd".
   "next_state_logic" is an NCD, version 2.38, device xc3s200, package ft256,
speed -4
Loading device for application Par from file '3s200.nph' in environment
C:/Program Files/Xilinx.
Device speed data version:  PRODUCTION 1.32 2004-06-25.


Device utilization summary:

   Number of External IOBs             8 out of 173     4%
      Number of LOCed External IOBs    0 out of 8       0%


   Number of BUFGMUXs                  1 out of 8      12%



Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)


Phase 1.1
Phase 1.1 (Checksum:989691) REAL time: 0 secs 

.
Phase 3.3
Phase 3.3 (Checksum:1c9c37d) REAL time: 0 secs 

Phase 4.5
Phase 4.5 (Checksum:26259fc) REAL time: 0 secs 

Phase 5.8
Phase 5.8 (Checksum:98b3cb) REAL time: 0 secs 

Phase 6.5
Phase 6.5 (Checksum:39386fa) REAL time: 0 secs 

Phase 7.18
Phase 7.18 (Checksum:42c1d79) REAL time: 0 secs 

Writing design to file next_state_logic.ncd.

Total REAL time to Placer completion: 0 secs 
Total CPU time to Placer completion: 0 secs 


Phase 1: 11 unrouted;       REAL time: 0 secs 

Phase 2: 7 unrouted;       REAL time: 0 secs 

Phase 3: 0 unrouted;       REAL time: 0 secs 

Phase 4: 0 unrouted;       REAL time: 0 secs 

Total REAL time to Router completion: 0 secs 
Total CPU time to Router completion: 0 secs 

Generating "par" statistics.

**************************
Generating Clock Report
**************************

+-------------------------+----------+------+------+------------+-------------+
|        Clock Net        | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+-------------------------+----------+------+------+------------+-------------+
|         clk_BUFGP       |  BUFGMUX3| No   |    3 |  0.001     |  1.051      |
+-------------------------+----------+------+------+------------+-------------+


   The Delay Summary Report

   The SCORE FOR THIS DESIGN is: 129


The NUMBER OF SIGNALS NOT COMPLETELY ROUTED for this design is: 0

   The AVERAGE CONNECTION DELAY for this design is:        1.147
   The MAXIMUM PIN DELAY IS:                               2.101
   The AVERAGE CONNECTION DELAY on the 10 WORST NETS is:   0.710

   Listing Pin Delays by value: (nsec)

    d < 1.00   < d < 2.00  < d < 3.00  < d < 4.00  < d < 5.00  d >= 5.00
   ---------   ---------   ---------   ---------   ---------   ---------
           2           8           1           0           0           0

Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 4 secs 
Total CPU time to PAR completion: 1 secs 

Peak Memory Usage:  55 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.

Writing design to file next_state_logic.ncd.


PAR done.