JDF G
// Created by Project Navigator ver 1.0
PROJECT esercitazione_2
DESIGN esercitazione_2
DEVFAM spartan3
DEVFAMTIME 0
DEVICE xc3s200
DEVICETIME 0
DEVPKG ft256
DEVPKGTIME 0
DEVSPEED -4
DEVSPEEDTIME 0
DEVTOPLEVELMODULETYPE HDL
TOPLEVELMODULETYPETIME 0
DEVSYNTHESISTOOL XST (VHDL/Verilog)
SYNTHESISTOOLTIME 0
DEVSIMULATOR Modelsim
SIMULATORTIME 0
DEVGENERATEDSIMULATIONMODEL VHDL
GENERATEDSIMULATIONMODELTIME 0
SOURCE next_state_logic.vhd
SOURCE datapath.vhd
SOURCE riconoscitore_1011.sch
STIMULUS tester.tbw
STIMULUS test_datapath.tbw
STIMULUS test_state.tbw
[STATUS-ALL]
riconoscitore_1011.ngcFile=WARNINGS,1174042774
[STRATEGY-LIST]
Normal=True