-- Xilinx Vhdl netlist produced by netgen application (version G.35)
-- Command       : -intstyle ise -s 4 -pcf datapath.pcf -ngm datapath.ngm -rpw 100 -tpw 0 -ar Structure -xon true -w -ofmt vhdl -sim datapath.ncd datapath_timesim.vhd 
-- Input file    : datapath.ncd
-- Output file   : datapath_timesim.vhd
-- Design name   : datapath
-- # of Entities : 1
-- Xilinx        : C:/Program Files/Xilinx
-- Device        : 3s200ft256-4 (PRODUCTION 1.32 2004-06-25)

-- This vhdl netlist is a simulation model and uses simulation 
-- primitives which may not represent the true implementation of the 
-- device, however the netlist is functionally correct and should not 
-- be modified. This file cannot be synthesized and should only be used 
-- with supported simulation tools.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library SIMPRIM;
use SIMPRIM.VCOMPONENTS.ALL;
use SIMPRIM.VPACKAGE.ALL;

entity datapath is
  port (
    y : out STD_LOGIC; 
    x : in STD_LOGIC := 'X'; 
    rst : in STD_LOGIC := 'X'; 
    en : in STD_LOGIC := 'X'; 
    clk : in STD_LOGIC := 'X'; 
    next_state : out STD_LOGIC_VECTOR ( 2 downto 0 ); 
    current_state : in STD_LOGIC_VECTOR ( 2 downto 0 ) 
  );
end datapath;

architecture Structure of datapath is
  signal en_IBUF : STD_LOGIC; 
  signal clk_BUFGP_IBUFG : STD_LOGIC; 
  signal x_IBUF : STD_LOGIC; 
  signal current_state_0_IBUF : STD_LOGIC; 
  signal current_state_1_IBUF : STD_LOGIC; 
  signal current_state_2_IBUF : STD_LOGIC; 
  signal y_OBUF : STD_LOGIC; 
  signal rst_IBUF : STD_LOGIC; 
  signal GLOBAL_LOGIC1 : STD_LOGIC; 
  signal clk_BUFGP : STD_LOGIC; 
  signal CHOICE164 : STD_LOGIC; 
  signal CHOICE188 : STD_LOGIC; 
  signal N1707 : STD_LOGIC; 
  signal N1705 : STD_LOGIC; 
  signal CHOICE170 : STD_LOGIC; 
  signal GSR : STD_LOGIC; 
  signal GTS : STD_LOGIC; 
  signal en_INBUF : STD_LOGIC; 
  signal clk_INBUF : STD_LOGIC; 
  signal x_INBUF : STD_LOGIC; 
  signal current_state_0_INBUF : STD_LOGIC; 
  signal current_state_1_INBUF : STD_LOGIC; 
  signal current_state_2_INBUF : STD_LOGIC; 
  signal next_state_0_ENABLE : STD_LOGIC; 
  signal next_state_0_GTS_OR_T : STD_LOGIC; 
  signal next_state_0_O : STD_LOGIC; 
  signal next_state_1_ENABLE : STD_LOGIC; 
  signal next_state_1_GTS_OR_T : STD_LOGIC; 
  signal next_state_1_O : STD_LOGIC; 
  signal next_state_2_ENABLE : STD_LOGIC; 
  signal next_state_2_GTS_OR_T : STD_LOGIC; 
  signal next_state_2_O : STD_LOGIC; 
  signal y_ENABLE : STD_LOGIC; 
  signal y_GTS_OR_T : STD_LOGIC; 
  signal y_O : STD_LOGIC; 
  signal rst_INBUF : STD_LOGIC; 
  signal clk_BUFGP_BUFG_S_INVNOT : STD_LOGIC; 
  signal y_OBUF_F : STD_LOGIC; 
  signal y_OBUF_DYMUX : STD_LOGIC; 
  signal Q_n00041_O : STD_LOGIC; 
  signal y_OBUF_SRINV : STD_LOGIC; 
  signal y_OBUF_CLKINV : STD_LOGIC; 
  signal y_OBUF_CEINV : STD_LOGIC; 
  signal nstate_0_DXMUX : STD_LOGIC; 
  signal Q_n0003_0_64_O : STD_LOGIC; 
  signal nstate_0_G : STD_LOGIC; 
  signal nstate_0_SRINV : STD_LOGIC; 
  signal nstate_0_CLKINV : STD_LOGIC; 
  signal nstate_0_CEINV : STD_LOGIC; 
  signal nstate_1_DXMUX : STD_LOGIC; 
  signal Q_n0003_1_70_O : STD_LOGIC; 
  signal nstate_1_G : STD_LOGIC; 
  signal nstate_1_SRINV : STD_LOGIC; 
  signal nstate_1_CLKINV : STD_LOGIC; 
  signal nstate_1_CEINV : STD_LOGIC; 
  signal nstate_2_DXMUX : STD_LOGIC; 
  signal Q_n0003_2_52_O : STD_LOGIC; 
  signal nstate_2_G : STD_LOGIC; 
  signal nstate_2_SRINV : STD_LOGIC; 
  signal nstate_2_CLKINV : STD_LOGIC; 
  signal nstate_2_CEINV : STD_LOGIC; 
  signal N1707_F : STD_LOGIC; 
  signal GND : STD_LOGIC; 
  signal VCC : STD_LOGIC; 
  signal nstate : STD_LOGIC_VECTOR ( 2 downto 0 ); 
begin
  en_IBUF_0 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => en,
      O => en_INBUF
    );
  clk_BUFGP_IBUFG_1 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => clk,
      O => clk_INBUF
    );
  x_IBUF_2 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => x,
      O => x_INBUF
    );
  current_state_0_IBUF_3 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => current_state(0),
      O => current_state_0_INBUF
    );
  current_state_1_IBUF_4 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => current_state(1),
      O => current_state_1_INBUF
    );
  current_state_2_IBUF_5 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => current_state(2),
      O => current_state_2_INBUF
    );
  next_state_0_OBUF : X_TRI_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => next_state_0_O,
      CTL => next_state_0_ENABLE,
      O => next_state(0)
    );
  next_state_0_ENABLEINV : X_INV
    port map (
      I => next_state_0_GTS_OR_T,
      O => next_state_0_ENABLE
    );
  next_state_0_GTS_OR_T_6 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => GTS,
      O => next_state_0_GTS_OR_T
    );
  next_state_1_OBUF : X_TRI_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => next_state_1_O,
      CTL => next_state_1_ENABLE,
      O => next_state(1)
    );
  next_state_1_ENABLEINV : X_INV
    port map (
      I => next_state_1_GTS_OR_T,
      O => next_state_1_ENABLE
    );
  next_state_1_GTS_OR_T_7 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => GTS,
      O => next_state_1_GTS_OR_T
    );
  next_state_2_OBUF : X_TRI_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => next_state_2_O,
      CTL => next_state_2_ENABLE,
      O => next_state(2)
    );
  next_state_2_ENABLEINV : X_INV
    port map (
      I => next_state_2_GTS_OR_T,
      O => next_state_2_ENABLE
    );
  next_state_2_GTS_OR_T_8 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => GTS,
      O => next_state_2_GTS_OR_T
    );
  y_OBUF_9 : X_TRI_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => y_O,
      CTL => y_ENABLE,
      O => y
    );
  y_ENABLEINV : X_INV
    port map (
      I => y_GTS_OR_T,
      O => y_ENABLE
    );
  y_GTS_OR_T_10 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => GTS,
      O => y_GTS_OR_T
    );
  rst_IBUF_11 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => rst,
      O => rst_INBUF
    );
  clk_BUFGP_BUFG : X_BUFGMUX
    port map (
      I0 => clk_BUFGP_IBUFG,
      I1 => GND,
      S => clk_BUFGP_BUFG_S_INVNOT,
      O => clk_BUFGP,
      GSR => GSR
    );
  clk_BUFGP_BUFG_SINV : X_INV
    port map (
      I => GLOBAL_LOGIC1,
      O => clk_BUFGP_BUFG_S_INVNOT
    );
  Q_n0003_2_29 : X_LUT4
    generic map(
      INIT => X"C0F9"
    )
    port map (
      ADR0 => x_IBUF,
      ADR1 => current_state_0_IBUF,
      ADR2 => current_state_2_IBUF,
      ADR3 => current_state_1_IBUF,
      O => y_OBUF_F
    );
  y_12 : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => y_OBUF_DYMUX,
      CE => y_OBUF_CEINV,
      CLK => y_OBUF_CLKINV,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => y_OBUF_SRINV,
      O => y_OBUF
    );
  Q_n00041 : X_LUT4
    generic map(
      INIT => X"A2A0"
    )
    port map (
      ADR0 => current_state_2_IBUF,
      ADR1 => current_state_0_IBUF,
      ADR2 => y_OBUF,
      ADR3 => current_state_1_IBUF,
      O => Q_n00041_O
    );
  y_OBUF_XUSED : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => y_OBUF_F,
      O => CHOICE164
    );
  y_OBUF_DYMUX_13 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => Q_n00041_O,
      O => y_OBUF_DYMUX
    );
  y_OBUF_SRINV_14 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => rst_IBUF,
      O => y_OBUF_SRINV
    );
  y_OBUF_CLKINV_15 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => clk_BUFGP,
      O => y_OBUF_CLKINV
    );
  y_OBUF_CEINV_16 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => en_IBUF,
      O => y_OBUF_CEINV
    );
  nstate_0 : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => nstate_0_DXMUX,
      CE => nstate_0_CEINV,
      CLK => nstate_0_CLKINV,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => nstate_0_SRINV,
      O => nstate(0)
    );
  Q_n0003_0_64 : X_LUT4
    generic map(
      INIT => X"FDF0"
    )
    port map (
      ADR0 => current_state_1_IBUF,
      ADR1 => current_state_2_IBUF,
      ADR2 => CHOICE188,
      ADR3 => nstate(0),
      O => Q_n0003_0_64_O
    );
  Q_n0003_0_56 : X_LUT4
    generic map(
      INIT => X"091A"
    )
    port map (
      ADR0 => current_state_1_IBUF,
      ADR1 => current_state_2_IBUF,
      ADR2 => current_state_0_IBUF,
      ADR3 => x_IBUF,
      O => nstate_0_G
    );
  nstate_0_DXMUX_17 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => Q_n0003_0_64_O,
      O => nstate_0_DXMUX
    );
  nstate_0_YUSED : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => nstate_0_G,
      O => CHOICE188
    );
  nstate_0_SRINV_18 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => rst_IBUF,
      O => nstate_0_SRINV
    );
  nstate_0_CLKINV_19 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => clk_BUFGP,
      O => nstate_0_CLKINV
    );
  nstate_0_CEINV_20 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => en_IBUF,
      O => nstate_0_CEINV
    );
  Q_n0003_1_70 : X_LUT4
    generic map(
      INIT => X"CCF0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => N1707,
      ADR2 => N1705,
      ADR3 => nstate(1),
      O => Q_n0003_1_70_O
    );
  Q_n0003_1_70_SW2 : X_LUT4
    generic map(
      INIT => X"221A"
    )
    port map (
      ADR0 => current_state_1_IBUF,
      ADR1 => current_state_2_IBUF,
      ADR2 => current_state_0_IBUF,
      ADR3 => x_IBUF,
      O => nstate_1_G
    );
  nstate_1_DXMUX_21 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => Q_n0003_1_70_O,
      O => nstate_1_DXMUX
    );
  nstate_1_YUSED : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => nstate_1_G,
      O => N1705
    );
  nstate_1_SRINV_22 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => rst_IBUF,
      O => nstate_1_SRINV
    );
  nstate_1_CLKINV_23 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => clk_BUFGP,
      O => nstate_1_CLKINV
    );
  nstate_1_CEINV_24 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => en_IBUF,
      O => nstate_1_CEINV
    );
  nstate_2_DXMUX_25 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => Q_n0003_2_52_O,
      O => nstate_2_DXMUX
    );
  nstate_2_YUSED : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => nstate_2_G,
      O => CHOICE170
    );
  nstate_2_SRINV_26 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => rst_IBUF,
      O => nstate_2_SRINV
    );
  nstate_2_CLKINV_27 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => clk_BUFGP,
      O => nstate_2_CLKINV
    );
  nstate_2_CEINV_28 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => en_IBUF,
      O => nstate_2_CEINV
    );
  Q_n0003_1_70_SW3 : X_LUT4
    generic map(
      INIT => X"F6BF"
    )
    port map (
      ADR0 => current_state_2_IBUF,
      ADR1 => current_state_1_IBUF,
      ADR2 => current_state_0_IBUF,
      ADR3 => x_IBUF,
      O => N1707_F
    );
  N1707_XUSED : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => N1707_F,
      O => N1707
    );
  nstate_1 : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => nstate_1_DXMUX,
      CE => nstate_1_CEINV,
      CLK => nstate_1_CLKINV,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => nstate_1_SRINV,
      O => nstate(1)
    );
  Q_n0003_2_50 : X_LUT4
    generic map(
      INIT => X"0200"
    )
    port map (
      ADR0 => x_IBUF,
      ADR1 => current_state_0_IBUF,
      ADR2 => current_state_2_IBUF,
      ADR3 => current_state_1_IBUF,
      O => nstate_2_G
    );
  Q_n0003_2_52 : X_LUT4
    generic map(
      INIT => X"FAF0"
    )
    port map (
      ADR0 => CHOICE164,
      ADR1 => VCC,
      ADR2 => CHOICE170,
      ADR3 => nstate(2),
      O => Q_n0003_2_52_O
    );
  nstate_2 : X_SFF
    generic map(
      INIT => '0'
    )
    port map (
      I => nstate_2_DXMUX,
      CE => nstate_2_CEINV,
      CLK => nstate_2_CLKINV,
      SET => GND,
      RST => GSR,
      SSET => GND,
      SRST => nstate_2_SRINV,
      O => nstate(2)
    );
  PWR_VCC_0_LOGICAL_ONE : X_ONE
    port map (
      O => GLOBAL_LOGIC1
    );
  en_IFF_IMUX : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => en_INBUF,
      O => en_IBUF
    );
  clk_IFF_IMUX : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => clk_INBUF,
      O => clk_BUFGP_IBUFG
    );
  x_IFF_IMUX : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => x_INBUF,
      O => x_IBUF
    );
  current_state_0_IFF_IMUX : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => current_state_0_INBUF,
      O => current_state_0_IBUF
    );
  current_state_1_IFF_IMUX : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => current_state_1_INBUF,
      O => current_state_1_IBUF
    );
  current_state_2_IFF_IMUX : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => current_state_2_INBUF,
      O => current_state_2_IBUF
    );
  next_state_0_OUTPUT_OFF_OMUX : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => nstate(0),
      O => next_state_0_O
    );
  next_state_1_OUTPUT_OFF_OMUX : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => nstate(1),
      O => next_state_1_O
    );
  next_state_2_OUTPUT_OFF_OMUX : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => nstate(2),
      O => next_state_2_O
    );
  y_OUTPUT_OFF_OMUX : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => y_OBUF,
      O => y_O
    );
  rst_IFF_IMUX : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => rst_INBUF,
      O => rst_IBUF
    );
  NlwBlock_datapath_GND : X_ZERO
    port map (
      O => GND
    );
  NlwBlock_datapath_VCC : X_ONE
    port map (
      O => VCC
    );
  NlwBlockROC : X_ROC
    generic map (ROC_WIDTH => 100 ns)
    port map (O => GSR);
  NlwBlockTOC : X_TOC
    port map (O => GTS);

end Structure;