library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarationstate that are
--  provided for instatetantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity datapath is
Port (clk,en,rst,x:in std_logic;
	 y:out std_logic;
	 current_state:in std_logic_vector(2 downto 0); 
	 next_state:out std_logic_vector(2 downto 0));
end datapath;
architecture Behavioral of datapath is


begin
process(current_state)
	variable nstate:std_logic_vector(2 downto 0):=current_state;
	--variable u:std_logic:='0';
	begin

	--if clk'event and clk='1' then
		--if rst='1' then
		--	nstate:="000";
		--	y<='0';
		if en = '1' then
			case current_state is
			when "000" => -- xxxx
				y<='0';
				if x='1' then
					nstate:="001";
				--else
				--	nstate<=current_state;
				end if;
			when "001" => -- 1xxx
				y<='0';
				if x='0' then
					nstate:="011";
				--else
				--	nstate<=current_state;
				end if;
			when "011" => -- 10xx
				y<='0';
				if x='0' then
					nstate:="000";
				else
					nstate:="010";
				end if;
			when "010" => -- 101x
				y<='0';
				if x='0' then
					nstate:="011";
				else
					nstate:="110";
				end if;
			when "110" => -- 1011
				y<='1';
				if x='0' then
					nstate:="011";
				else
					nstate:="001";
				end if;
			when others => null;
			end case;
		end if;
	--end if;
	next_state<=nstate;
	--y<=u;
end process;
end Behavioral;