Project Navigator Auto-Make Log File ------------------------------------- Started process "Check Syntax". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file Z:/camurati/esercitazione_2/next_state_logic.vhd in Library work. ERROR:HDLParsers:164 - Z:/camurati/esercitazione_2/next_state_logic.vhd Line 17. parse error, unexpected EQ, expecting COMMA or COLON ERROR:HDLParsers:3260 - Z:/camurati/esercitazione_2/next_state_logic.vhd Line 26. Object name expected: physical literal 'ns' unexpected. ERROR:HDLParsers:3260 - Z:/camurati/esercitazione_2/next_state_logic.vhd Line 28. Object name expected: physical literal 'ns' unexpected. ERROR:HDLParsers:800 - Z:/camurati/esercitazione_2/next_state_logic.vhd Line 32. Type of state_out is incompatible with type of ns. ERROR: XST failed Process "Check Syntax" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Check Syntax". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file Z:/camurati/esercitazione_2/next_state_logic.vhd in Library work. Entity (Architecture ) compiled. Completed process "Check Syntax". Project Navigator Auto-Make Log File ------------------------------------- Started process "Check Syntax". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file Z:/camurati/esercitazione_2/next_state_logic.vhd in Library work. Entity (Architecture ) compiled. Completed process "Check Syntax". Project Navigator Auto-Make Log File ------------------------------------- Started process "Create Schematic Symbol". Compiling vhdl file Z:/camurati/esercitazione_2/next_state_logic.vhd in Library work. Entity (Architecture ) compiled. tdtfi(vhdl) completed successfully. Release 6.3i - spl2sym G.35 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. Completed process "Create Schematic Symbol". Project Navigator Auto-Make Log File ------------------------------------- Started process "Check Syntax". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file Z:/camurati/esercitazione_2/datapath.vhd in Library work. ERROR:HDLParsers:164 - Z:/camurati/esercitazione_2/datapath.vhd Line 14. parse error, unexpected SIGNAL ERROR: XST failed Process "Check Syntax" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Check Syntax". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file Z:/camurati/esercitazione_2/datapath.vhd in Library work. ERROR:HDLParsers:3402 - Z:/camurati/esercitazione_2/datapath.vhd Line 23. Read symbol =, expecting <= or := ERROR:HDLParsers:164 - Z:/camurati/esercitazione_2/datapath.vhd Line 26. parse error, unexpected IDENTIFIER, expecting THEN ERROR:HDLParsers:164 - Z:/camurati/esercitazione_2/datapath.vhd Line 36. parse error, unexpected WHEN, expecting END ERROR:HDLParsers:164 - Z:/camurati/esercitazione_2/datapath.vhd Line 43. parse error, unexpected WHEN, expecting END ERROR:HDLParsers:164 - Z:/camurati/esercitazione_2/datapath.vhd Line 50. parse error, unexpected WHEN, expecting END ERROR:HDLParsers:3402 - Z:/camurati/esercitazione_2/datapath.vhd Line 53. Read symbol =, expecting <= or := ERROR:HDLParsers:164 - Z:/camurati/esercitazione_2/datapath.vhd Line 58. parse error, unexpected WHEN, expecting END ERROR:HDLParsers:164 - Z:/camurati/esercitazione_2/datapath.vhd Line 61. parse error, unexpected IF, expecting PROCESS ERROR: XST failed Process "Check Syntax" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Check Syntax". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file Z:/camurati/esercitazione_2/datapath.vhd in Library work. ERROR:HDLParsers:164 - Z:/camurati/esercitazione_2/datapath.vhd Line 26. parse error, unexpected IDENTIFIER, expecting THEN ERROR:HDLParsers:164 - Z:/camurati/esercitazione_2/datapath.vhd Line 36. parse error, unexpected WHEN, expecting END ERROR:HDLParsers:164 - Z:/camurati/esercitazione_2/datapath.vhd Line 43. parse error, unexpected WHEN, expecting END ERROR:HDLParsers:164 - Z:/camurati/esercitazione_2/datapath.vhd Line 50. parse error, unexpected WHEN, expecting END ERROR:HDLParsers:3402 - Z:/camurati/esercitazione_2/datapath.vhd Line 53. Read symbol =, expecting <= or := ERROR:HDLParsers:164 - Z:/camurati/esercitazione_2/datapath.vhd Line 58. parse error, unexpected WHEN, expecting END ERROR:HDLParsers:164 - Z:/camurati/esercitazione_2/datapath.vhd Line 61. parse error, unexpected IF, expecting PROCESS ERROR: XST failed Process "Check Syntax" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Check Syntax". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file Z:/camurati/esercitazione_2/datapath.vhd in Library work. ERROR:HDLParsers:3402 - Z:/camurati/esercitazione_2/datapath.vhd Line 53. Read symbol =, expecting <= or := ERROR: XST failed Process "Check Syntax" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Check Syntax". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file Z:/camurati/esercitazione_2/datapath.vhd in Library work. Entity (Architecture ) compiled. Completed process "Check Syntax". Project Navigator Auto-Make Log File ------------------------------------- Started process "Create Schematic Symbol". Compiling vhdl file Z:/camurati/esercitazione_2/datapath.vhd in Library work. Entity (Architecture ) compiled. tdtfi(vhdl) completed successfully. Release 6.3i - spl2sym G.35 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. Completed process "Create Schematic Symbol". Project Navigator Auto-Make Log File ------------------------------------- Started process "View VHDL Functional Model". Release 6.3i - sch2vhdl G.35 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. WARNING:DesignEntry:16 - Bus "XLXN_1(1:0)" is connected to source pins and/or IO ports while there is no load pin connected to it WARNING:DesignEntry:14 - Bus "XLXN_3(1:0)" is connected to load pins and/or IO Ports, but there is no source pin or IO Port connected to it DRC Check completed: No Error found. Vhdl netlist file generated. Completed process "View VHDL Functional Model". Project Navigator Auto-Make Log File ------------------------------------- Launching Application for process "Generate Expected Simulation Results". Reading c:/program files/Modeltech_xe_starter/win32xoem/../tcl/vsim/pref.tcl # 5.8c # do tester_riconoscitore.ado listening on address 127.0.0.1 port 1200 # resume # Model Technology ModelSim XE II vcom 5.8c Compiler 2004.03 Mar 26 2004 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity datapath # -- Compiling architecture behavioral of datapath # Model Technology ModelSim XE II vcom 5.8c Compiler 2004.03 Mar 26 2004 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity next_state_logic # -- Compiling architecture behavioral of next_state_logic # Model Technology ModelSim XE II vcom 5.8c Compiler 2004.03 Mar 26 2004 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package numeric_std # -- Loading package vital_timing # -- Loading package vcomponents # -- Compiling entity riconoscitore_1011 # -- Compiling architecture behavioral of riconoscitore_1011 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading entity datapath # -- Loading entity next_state_logic # Model Technology ModelSim XE II vcom 5.8c Compiler 2004.03 Mar 26 2004 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package numeric_std # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity tester_riconoscitore # -- Compiling architecture testbench_arch of tester_riconoscitore # -- Loading package vital_timing # -- Loading package vcomponents # -- Loading entity riconoscitore_1011 # -- Compiling configuration riconoscitore_1011_cfg # -- Loading entity tester_riconoscitore # -- Loading architecture testbench_arch of tester_riconoscitore # vsim -lib work -t 1ps tester_riconoscitore # Loading c:\program files\Modeltech_xe_starter\win32xoem/../std.standard # Loading c:\program files\Modeltech_xe_starter\win32xoem/../ieee.std_logic_1164(body) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../ieee.numeric_std(body) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../std.textio(body) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../ieee.std_logic_textio(body) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../ieee.vital_timing(body) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../xilinx/vhdl/unisim.vcomponents # Loading work.tester_riconoscitore(testbench_arch) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../ieee.std_logic_arith(body) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../ieee.std_logic_unsigned(body) # Loading work.riconoscitore_1011(behavioral) # Loading work.datapath(behavioral) # Loading work.next_state_logic(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 1410 ns Iteration: 0 Process: /tester_riconoscitore/line__85 File: tester_riconoscitore.ant # Break at tester_riconoscitore.ant line 127 # Stopped at tester_riconoscitore.ant line 127 Project Navigator Auto-Make Log File ------------------------------------- Launching Application for process "Generate Expected Simulation Results". Reading c:/program files/Modeltech_xe_starter/win32xoem/../tcl/vsim/pref.tcl # 5.8c # do tester_riconoscitore.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.8c Compiler 2004.03 Mar 26 2004 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity datapath # -- Compiling architecture behavioral of datapath # Model Technology ModelSim XE II vcom 5.8c Compiler 2004.03 Mar 26 2004 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity next_state_logic # -- Compiling architecture behavioral of next_state_logic # Model Technology ModelSim XE II vcom 5.8c Compiler 2004.03 Mar 26 2004 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package numeric_std # -- Loading package vital_timing # -- Loading package vcomponents # -- Compiling entity riconoscitore_1011 # -- Compiling architecture behavioral of riconoscitore_1011 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading entity datapath # -- Loading entity next_state_logic # Model Technology ModelSim XE II vcom 5.8c Compiler 2004.03 Mar 26 2004 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package numeric_std # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity tester_riconoscitore # -- Compiling architecture testbench_arch of tester_riconoscitore # -- Loading package vital_timing # -- Loading package vcomponents # -- Loading entity riconoscitore_1011 # -- Compiling configuration riconoscitore_1011_cfg # -- Loading entity tester_riconoscitore # -- Loading architecture testbench_arch of tester_riconoscitore # vsim -lib work -t 1ps tester_riconoscitore # Loading c:\program files\Modeltech_xe_starter\win32xoem/../std.standard # Loading c:\program files\Modeltech_xe_starter\win32xoem/../ieee.std_logic_1164(body) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../ieee.numeric_std(body) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../std.textio(body) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../ieee.std_logic_textio(body) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../ieee.vital_timing(body) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../xilinx/vhdl/unisim.vcomponents # Loading work.tester_riconoscitore(testbench_arch) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../ieee.std_logic_arith(body) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../ieee.std_logic_unsigned(body) # Loading work.riconoscitore_1011(behavioral) # Loading work.datapath(behavioral) # Loading work.next_state_logic(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 1410 ns Iteration: 0 Process: /tester_riconoscitore/line__85 File: tester_riconoscitore.ant # Break at tester_riconoscitore.ant line 127 # Stopped at tester_riconoscitore.ant line 127 Project Navigator Auto-Make Log File ------------------------------------- Launching Application for process "Generate Expected Simulation Results". Reading c:/program files/Modeltech_xe_starter/win32xoem/../tcl/vsim/pref.tcl # 5.8c # do tester_riconoscitore.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.8c Compiler 2004.03 Mar 26 2004 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity datapath # -- Compiling architecture behavioral of datapath # Model Technology ModelSim XE II vcom 5.8c Compiler 2004.03 Mar 26 2004 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity next_state_logic # -- Compiling architecture behavioral of next_state_logic # Model Technology ModelSim XE II vcom 5.8c Compiler 2004.03 Mar 26 2004 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package numeric_std # -- Loading package vital_timing # -- Loading package vcomponents # -- Compiling entity riconoscitore_1011 # -- Compiling architecture behavioral of riconoscitore_1011 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading entity datapath # -- Loading entity next_state_logic # Model Technology ModelSim XE II vcom 5.8c Compiler 2004.03 Mar 26 2004 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package numeric_std # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity tester_riconoscitore # -- Compiling architecture testbench_arch of tester_riconoscitore # -- Loading package vital_timing # -- Loading package vcomponents # -- Loading entity riconoscitore_1011 # -- Compiling configuration riconoscitore_1011_cfg # -- Loading entity tester_riconoscitore # -- Loading architecture testbench_arch of tester_riconoscitore # vsim -lib work -t 1ps tester_riconoscitore # Loading c:\program files\Modeltech_xe_starter\win32xoem/../std.standard # Loading c:\program files\Modeltech_xe_starter\win32xoem/../ieee.std_logic_1164(body) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../ieee.numeric_std(body) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../std.textio(body) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../ieee.std_logic_textio(body) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../ieee.vital_timing(body) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../xilinx/vhdl/unisim.vcomponents # Loading work.tester_riconoscitore(testbench_arch) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../ieee.std_logic_arith(body) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../ieee.std_logic_unsigned(body) # Loading work.riconoscitore_1011(behavioral) # Loading work.datapath(behavioral) # Loading work.next_state_logic(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 1410 ms Iteration: 0 Process: /tester_riconoscitore/line__85 File: tester_riconoscitore.ant # Break at tester_riconoscitore.ant line 127 # Stopped at tester_riconoscitore.ant line 127 Project Navigator Auto-Make Log File ------------------------------------- Launching Application for process "Generate Expected Simulation Results". Reading c:/program files/Modeltech_xe_starter/win32xoem/../tcl/vsim/pref.tcl # 5.8c # do tester_riconoscitore.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.8c Compiler 2004.03 Mar 26 2004 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity datapath # -- Compiling architecture behavioral of datapath # Model Technology ModelSim XE II vcom 5.8c Compiler 2004.03 Mar 26 2004 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity next_state_logic # -- Compiling architecture behavioral of next_state_logic # Model Technology ModelSim XE II vcom 5.8c Compiler 2004.03 Mar 26 2004 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package numeric_std # -- Loading package vital_timing # -- Loading package vcomponents # -- Compiling entity riconoscitore_1011 # -- Compiling architecture behavioral of riconoscitore_1011 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading entity datapath # -- Loading entity next_state_logic # Model Technology ModelSim XE II vcom 5.8c Compiler 2004.03 Mar 26 2004 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package numeric_std # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity tester_riconoscitore # -- Compiling architecture testbench_arch of tester_riconoscitore # -- Loading package vital_timing # -- Loading package vcomponents # -- Loading entity riconoscitore_1011 # -- Compiling configuration riconoscitore_1011_cfg # -- Loading entity tester_riconoscitore # -- Loading architecture testbench_arch of tester_riconoscitore # vsim -lib work -t 1ps tester_riconoscitore # Loading c:\program files\Modeltech_xe_starter\win32xoem/../std.standard # Loading c:\program files\Modeltech_xe_starter\win32xoem/../ieee.std_logic_1164(body) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../ieee.numeric_std(body) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../std.textio(body) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../ieee.std_logic_textio(body) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../ieee.vital_timing(body) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../xilinx/vhdl/unisim.vcomponents # Loading work.tester_riconoscitore(testbench_arch) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../ieee.std_logic_arith(body) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../ieee.std_logic_unsigned(body) # Loading work.riconoscitore_1011(behavioral) # Loading work.datapath(behavioral) # Loading work.next_state_logic(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 1410 ms Iteration: 0 Process: /tester_riconoscitore/line__85 File: tester_riconoscitore.ant # Break at tester_riconoscitore.ant line 127 # Stopped at tester_riconoscitore.ant line 127 Project Navigator Auto-Make Log File ------------------------------------- Launching Application for process "Generate Expected Simulation Results". Reading c:/program files/Modeltech_xe_starter/win32xoem/../tcl/vsim/pref.tcl # 5.8c # do tester_riconoscitore.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.8c Compiler 2004.03 Mar 26 2004 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity datapath # -- Compiling architecture behavioral of datapath # Model Technology ModelSim XE II vcom 5.8c Compiler 2004.03 Mar 26 2004 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity next_state_logic # -- Compiling architecture behavioral of next_state_logic # Model Technology ModelSim XE II vcom 5.8c Compiler 2004.03 Mar 26 2004 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package numeric_std # -- Loading package vital_timing # -- Loading package vcomponents # -- Compiling entity riconoscitore_1011 # -- Compiling architecture behavioral of riconoscitore_1011 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading entity datapath # -- Loading entity next_state_logic # Model Technology ModelSim XE II vcom 5.8c Compiler 2004.03 Mar 26 2004 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package numeric_std # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity tester_riconoscitore # -- Compiling architecture testbench_arch of tester_riconoscitore # -- Loading package vital_timing # -- Loading package vcomponents # -- Loading entity riconoscitore_1011 # -- Compiling configuration riconoscitore_1011_cfg # -- Loading entity tester_riconoscitore # -- Loading architecture testbench_arch of tester_riconoscitore # vsim -lib work -t 1ps tester_riconoscitore # Loading c:\program files\Modeltech_xe_starter\win32xoem/../std.standard # Loading c:\program files\Modeltech_xe_starter\win32xoem/../ieee.std_logic_1164(body) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../ieee.numeric_std(body) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../std.textio(body) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../ieee.std_logic_textio(body) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../ieee.vital_timing(body) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../xilinx/vhdl/unisim.vcomponents # Loading work.tester_riconoscitore(testbench_arch) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../ieee.std_logic_arith(body) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../ieee.std_logic_unsigned(body) # Loading work.riconoscitore_1011(behavioral) # Loading work.datapath(behavioral) # Loading work.next_state_logic(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 1410 us Iteration: 0 Process: /tester_riconoscitore/line__85 File: tester_riconoscitore.ant # Break at tester_riconoscitore.ant line 127 # Stopped at tester_riconoscitore.ant line 127 Project Navigator Auto-Make Log File ------------------------------------- Launching Application for process "Generate Expected Simulation Results". Reading c:/program files/Modeltech_xe_starter/win32xoem/../tcl/vsim/pref.tcl # 5.8c # do tester.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.8c Compiler 2004.03 Mar 26 2004 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity datapath # -- Compiling architecture behavioral of datapath # Model Technology ModelSim XE II vcom 5.8c Compiler 2004.03 Mar 26 2004 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity next_state_logic # -- Compiling architecture behavioral of next_state_logic # Model Technology ModelSim XE II vcom 5.8c Compiler 2004.03 Mar 26 2004 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package numeric_std # -- Loading package vital_timing # -- Loading package vcomponents # -- Compiling entity riconoscitore_1011 # -- Compiling architecture behavioral of riconoscitore_1011 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading entity datapath # -- Loading entity next_state_logic # Model Technology ModelSim XE II vcom 5.8c Compiler 2004.03 Mar 26 2004 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package numeric_std # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity tester # -- Compiling architecture testbench_arch of tester # -- Loading package vital_timing # -- Loading package vcomponents # -- Loading entity riconoscitore_1011 # -- Compiling configuration riconoscitore_1011_cfg # -- Loading entity tester # -- Loading architecture testbench_arch of tester # vsim -lib work -t 1ps tester # Loading c:\program files\Modeltech_xe_starter\win32xoem/../std.standard # Loading c:\program files\Modeltech_xe_starter\win32xoem/../ieee.std_logic_1164(body) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../ieee.numeric_std(body) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../std.textio(body) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../ieee.std_logic_textio(body) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../ieee.vital_timing(body) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../xilinx/vhdl/unisim.vcomponents # Loading work.tester(testbench_arch) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../ieee.std_logic_arith(body) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../ieee.std_logic_unsigned(body) # Loading work.riconoscitore_1011(behavioral) # Loading work.datapath(behavioral) # Loading work.next_state_logic(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 910 ms Iteration: 0 Process: /tester/line__85 File: tester.ant # Break at tester.ant line 115 # Stopped at tester.ant line 115 Project Navigator Auto-Make Log File ------------------------------------- Launching Application for process "Generate Expected Simulation Results". Reading c:/program files/Modeltech_xe_starter/win32xoem/../tcl/vsim/pref.tcl # 5.8c # do tester.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.8c Compiler 2004.03 Mar 26 2004 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity datapath # -- Compiling architecture behavioral of datapath # Model Technology ModelSim XE II vcom 5.8c Compiler 2004.03 Mar 26 2004 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity next_state_logic # -- Compiling architecture behavioral of next_state_logic # Model Technology ModelSim XE II vcom 5.8c Compiler 2004.03 Mar 26 2004 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package numeric_std # -- Loading package vital_timing # -- Loading package vcomponents # -- Compiling entity riconoscitore_1011 # -- Compiling architecture behavioral of riconoscitore_1011 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading entity datapath # -- Loading entity next_state_logic # Model Technology ModelSim XE II vcom 5.8c Compiler 2004.03 Mar 26 2004 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package numeric_std # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity tester # -- Compiling architecture testbench_arch of tester # -- Loading package vital_timing # -- Loading package vcomponents # -- Loading entity riconoscitore_1011 # -- Compiling configuration riconoscitore_1011_cfg # -- Loading entity tester # -- Loading architecture testbench_arch of tester # vsim -lib work -t 1ps tester # Loading c:\program files\Modeltech_xe_starter\win32xoem/../std.standard # Loading c:\program files\Modeltech_xe_starter\win32xoem/../ieee.std_logic_1164(body) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../ieee.numeric_std(body) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../std.textio(body) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../ieee.std_logic_textio(body) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../ieee.vital_timing(body) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../xilinx/vhdl/unisim.vcomponents # Loading work.tester(testbench_arch) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../ieee.std_logic_arith(body) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../ieee.std_logic_unsigned(body) # Loading work.riconoscitore_1011(behavioral) # Loading work.datapath(behavioral) # Loading work.next_state_logic(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 910 ms Iteration: 0 Process: /tester/line__85 File: tester.ant # Break at tester.ant line 112 # Stopped at tester.ant line 112 Project Navigator Auto-Make Log File ------------------------------------- Launching Application for process "Generate Expected Simulation Results". Reading c:/program files/Modeltech_xe_starter/win32xoem/../tcl/vsim/pref.tcl # 5.8c # do tester.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.8c Compiler 2004.03 Mar 26 2004 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity datapath # -- Compiling architecture behavioral of datapath # Model Technology ModelSim XE II vcom 5.8c Compiler 2004.03 Mar 26 2004 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity next_state_logic # -- Compiling architecture behavioral of next_state_logic # Model Technology ModelSim XE II vcom 5.8c Compiler 2004.03 Mar 26 2004 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package numeric_std # -- Loading package vital_timing # -- Loading package vcomponents # -- Compiling entity riconoscitore_1011 # -- Compiling architecture behavioral of riconoscitore_1011 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading entity datapath # -- Loading entity next_state_logic # Model Technology ModelSim XE II vcom 5.8c Compiler 2004.03 Mar 26 2004 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package numeric_std # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity tester # -- Compiling architecture testbench_arch of tester # -- Loading package vital_timing # -- Loading package vcomponents # -- Loading entity riconoscitore_1011 # -- Compiling configuration riconoscitore_1011_cfg # -- Loading entity tester # -- Loading architecture testbench_arch of tester # vsim -lib work -t 1ps tester # Loading c:\program files\Modeltech_xe_starter\win32xoem/../std.standard # Loading c:\program files\Modeltech_xe_starter\win32xoem/../ieee.std_logic_1164(body) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../ieee.numeric_std(body) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../std.textio(body) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../ieee.std_logic_textio(body) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../ieee.vital_timing(body) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../xilinx/vhdl/unisim.vcomponents # Loading work.tester(testbench_arch) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../ieee.std_logic_arith(body) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../ieee.std_logic_unsigned(body) # Loading work.riconoscitore_1011(behavioral) # Loading work.datapath(behavioral) # Loading work.next_state_logic(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 910 ms Iteration: 0 Process: /tester/line__85 File: tester.ant # Break at tester.ant line 115 # Stopped at tester.ant line 115 Project Navigator Auto-Make Log File ------------------------------------- Started process "Check Syntax". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file Z:/camurati/esercitazione_2/next_state_logic.vhd in Library work. Entity (Architecture ) compiled. Completed process "Check Syntax". Project Navigator Auto-Make Log File ------------------------------------- Started process "Check Syntax". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file Z:/camurati/esercitazione_2/datapath.vhd in Library work. Entity (Architecture ) compiled. Completed process "Check Syntax". Project Navigator Auto-Make Log File ------------------------------------- Started process "Create Schematic Symbol". Compiling vhdl file Z:/camurati/esercitazione_2/datapath.vhd in Library work. Entity (Architecture ) compiled. tdtfi(vhdl) completed successfully. Release 6.3i - spl2sym G.35 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. Completed process "Create Schematic Symbol". Project Navigator Auto-Make Log File ------------------------------------- Started process "Create Schematic Symbol". Compiling vhdl file Z:/camurati/esercitazione_2/next_state_logic.vhd in Library work. Entity (Architecture ) compiled. tdtfi(vhdl) completed successfully. Release 6.3i - spl2sym G.35 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. Completed process "Create Schematic Symbol". Project Navigator Auto-Make Log File ------------------------------------- Launching Application for process "Generate Expected Simulation Results". Reading c:/program files/Modeltech_xe_starter/win32xoem/../tcl/vsim/pref.tcl # 5.8c # do tester.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.8c Compiler 2004.03 Mar 26 2004 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity datapath # -- Compiling architecture behavioral of datapath # Model Technology ModelSim XE II vcom 5.8c Compiler 2004.03 Mar 26 2004 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity next_state_logic # -- Compiling architecture behavioral of next_state_logic # Model Technology ModelSim XE II vcom 5.8c Compiler 2004.03 Mar 26 2004 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package numeric_std # -- Loading package vital_timing # -- Loading package vcomponents # -- Compiling entity riconoscitore_1011 # -- Compiling architecture behavioral of riconoscitore_1011 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading entity datapath # -- Loading entity next_state_logic # Model Technology ModelSim XE II vcom 5.8c Compiler 2004.03 Mar 26 2004 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package numeric_std # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity tester # -- Compiling architecture testbench_arch of tester # -- Loading package vital_timing # -- Loading package vcomponents # -- Loading entity riconoscitore_1011 # -- Compiling configuration riconoscitore_1011_cfg # -- Loading entity tester # -- Loading architecture testbench_arch of tester # vsim -lib work -t 1ps tester # Loading c:\program files\Modeltech_xe_starter\win32xoem/../std.standard # Loading c:\program files\Modeltech_xe_starter\win32xoem/../ieee.std_logic_1164(body) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../ieee.numeric_std(body) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../std.textio(body) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../ieee.std_logic_textio(body) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../ieee.vital_timing(body) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../xilinx/vhdl/unisim.vcomponents # Loading work.tester(testbench_arch) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../ieee.std_logic_arith(body) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../ieee.std_logic_unsigned(body) # Loading work.riconoscitore_1011(behavioral) # Loading work.datapath(behavioral) # Loading work.next_state_logic(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 910 ms Iteration: 0 Process: /tester/line__85 File: tester.ant # Break at tester.ant line 115 # Stopped at tester.ant line 115 Project Navigator Auto-Make Log File ------------------------------------- Started process "View VHDL Functional Model". Release 6.3i - sch2vhdl G.35 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. WARNING:DesignEntry:16 - Bus "XLXN_1(1:0)" is connected to source pins and/or IO ports while there is no load pin connected to it WARNING:DesignEntry:14 - Bus "XLXN_3(1:0)" is connected to load pins and/or IO Ports, but there is no source pin or IO Port connected to it DRC Check completed: No Error found. Vhdl netlist file generated. Completed process "View VHDL Functional Model". Project Navigator Auto-Make Log File ------------------------------------- Launching Application for process "Generate Expected Simulation Results". Reading c:/program files/Modeltech_xe_starter/win32xoem/../tcl/vsim/pref.tcl # 5.8c # do tester.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.8c Compiler 2004.03 Mar 26 2004 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity datapath # -- Compiling architecture behavioral of datapath # Model Technology ModelSim XE II vcom 5.8c Compiler 2004.03 Mar 26 2004 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity next_state_logic # -- Compiling architecture behavioral of next_state_logic # Model Technology ModelSim XE II vcom 5.8c Compiler 2004.03 Mar 26 2004 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package numeric_std # -- Loading package vital_timing # -- Loading package vcomponents # -- Compiling entity riconoscitore_1011 # -- Compiling architecture behavioral of riconoscitore_1011 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading entity datapath # -- Loading entity next_state_logic # Model Technology ModelSim XE II vcom 5.8c Compiler 2004.03 Mar 26 2004 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package numeric_std # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity tester # -- Compiling architecture testbench_arch of tester # -- Loading package vital_timing # -- Loading package vcomponents # -- Loading entity riconoscitore_1011 # -- Compiling configuration riconoscitore_1011_cfg # -- Loading entity tester # -- Loading architecture testbench_arch of tester # vsim -lib work -t 1ps tester # Loading c:\program files\Modeltech_xe_starter\win32xoem/../std.standard # Loading c:\program files\Modeltech_xe_starter\win32xoem/../ieee.std_logic_1164(body) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../ieee.numeric_std(body) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../std.textio(body) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../ieee.std_logic_textio(body) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../ieee.vital_timing(body) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../xilinx/vhdl/unisim.vcomponents # Loading work.tester(testbench_arch) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../ieee.std_logic_arith(body) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../ieee.std_logic_unsigned(body) # Loading work.riconoscitore_1011(behavioral) # Loading work.datapath(behavioral) # Loading work.next_state_logic(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 910 ms Iteration: 0 Process: /tester/line__85 File: tester.ant # Break at tester.ant line 117 # Stopped at tester.ant line 117 Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file Z:/camurati/esercitazione_2/datapath.vhd in Library work. Architecture behavioral of Entity datapath is up to date. Compiling vhdl file Z:/camurati/esercitazione_2/next_state_logic.vhd in Library work. Architecture behavioral of Entity next_state_logic is up to date. Compiling vhdl file Z:/camurati/esercitazione_2/riconoscitore_1011.vhf in Library work. Architecture behavioral of Entity riconoscitore_1011 is up to date. ========================================================================= * HDL Analysis * ========================================================================= Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is Z:/camurati/esercitazione_2/next_state_logic.vhd. Found 2-bit register for signal . Summary: inferred 2 D-type flip-flop(s). Unit synthesized. Synthesizing Unit . Related source file is Z:/camurati/esercitazione_2/datapath.vhd. Found 2-bit register for signal . Found 1-bit register for signal . Summary: inferred 3 D-type flip-flop(s). Unit synthesized. Synthesizing Unit . Related source file is Z:/camurati/esercitazione_2/riconoscitore_1011.vhf. WARNING:Xst:646 - Signal is assigned but never used. WARNING:Xst:653 - Signal is used but never assigned. Tied to value 00. Unit synthesized. ========================================================================= * Advanced HDL Synthesis * ========================================================================= Advanced RAM inference ... Advanced multiplier inference ... Advanced Registered AddSub inference ... WARNING:Xst:524 - All outputs of the instance of the block are unconnected in block . This instance will be removed from the design along with all underlying logic Dynamic shift register inference ... ========================================================================= HDL Synthesis Report Macro Statistics # Registers : 2 1-bit register : 1 2-bit register : 1 ========================================================================= ========================================================================= * Low Level Synthesis * ========================================================================= WARNING:Xst:1291 - FF/Latch is unconnected in block . WARNING:Xst:1291 - FF/Latch is unconnected in block . Optimizing unit ... Optimizing unit ... Loading device for application Xst from file '3s200.nph' in environment C:/Program Files/Xilinx. Mapping all equations... WARNING:Xst:1293 - FF/Latch is constant in block . WARNING:Xst:1291 - FF/Latch is unconnected in block . WARNING:Xst:1291 - FF/Latch is unconnected in block . Building and optimizing final netlist ... Found area constraint ratio of 100 (+ 5) on block riconoscitore_1011, actual ratio is 0. ========================================================================= * Final Report * ========================================================================= Device utilization summary: --------------------------- Selected Device : 3s200ft256-4 Number of bonded IOBs: 1 out of 173 0% ========================================================================= TIMING REPORT Clock Information: ------------------ No clock signals found in this design Timing Summary: --------------- Speed Grade: -4 Minimum period: No path found Minimum input arrival time before clock: No path found Maximum output required time after clock: No path found Maximum combinational path delay: No path found ========================================================================= Completed process "Synthesize". Started process "Translate". Command Line: ngdbuild -intstyle ise -dd z:\camurati\esercitazione_2/_ngo -i -p xc3s200-ft256-4 riconoscitore_1011.ngc riconoscitore_1011.ngd Reading NGO file "Z:/camurati/esercitazione_2/riconoscitore_1011.ngc" ... Reading component libraries for design expansion... Checking timing specifications ... Checking expanded design ... NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0 Total memory usage is 38140 kilobytes Writing NGD file "riconoscitore_1011.ngd" ... Writing NGDBUILD log file "riconoscitore_1011.bld"... NGDBUILD done. Completed process "Translate". Started process "Map". Using target part "3s200ft256-4". Removing unused or disabled logic... Running cover... Running directed packing... Running delay-based LUT packing... Running related packing... Design Summary: Number of errors: 0 Number of warnings: 0 Logic Utilization: Logic Distribution: Number of Slices containing only related logic: 0 out of 0 0% Number of Slices containing unrelated logic: 0 out of 0 0% *See NOTES below for an explanation of the effects of unrelated logic Number of bonded IOBs: 1 out of 173 1% Total equivalent gate count for design: 0 Additional JTAG gate count for IOBs: 48 Peak Memory Usage: 66 MB NOTES: Related logic is defined as being logic that shares connectivity - e.g. two LUTs are "related" if they share common inputs. When assembling slices, Map gives priority to combine logic that is related. Doing so results in the best timing performance. Unrelated logic shares no connectivity. Map will only begin packing unrelated logic into a slice once 99% of the slices are occupied through related logic packing. Note that once logic distribution reaches the 99% level through related logic packing, this does not mean the device is completely utilized. Unrelated logic packing will then begin, continuing until all usable LUTs and FFs are occupied. Depending on your timing budget, increased levels of unrelated logic packing may adversely affect the overall timing performance of your design. Mapping completed. See MAP report file "riconoscitore_1011_map.mrp" for details. Completed process "Map". Mapping Module riconoscitore_1011 . . . MAP command line: map -intstyle ise -p xc3s200-ft256-4 -cm area -pr b -k 4 -c 100 -tx off -o riconoscitore_1011_map.ncd riconoscitore_1011.ngd riconoscitore_1011.pcf Mapping Module riconoscitore_1011: DONE Started process "Place & Route". Constraints file: riconoscitore_1011.pcf Loading device database for application Par from file "riconoscitore_1011_map.ncd". "riconoscitore_1011" is an NCD, version 2.38, device xc3s200, package ft256, speed -4 Loading device for application Par from file '3s200.nph' in environment C:/Program Files/Xilinx. Device speed data version: PRODUCTION 1.32 2004-06-25. Resolving physical constraints. Finished resolving physical constraints. Device utilization summary: Number of External IOBs 1 out of 173 1% Number of LOCed External IOBs 0 out of 1 0% Overall effort level (-ol): Standard (set by user) Placer effort level (-pl): Standard (set by user) Placer cost table entry (-t): 1 Router effort level (-rl): Standard (set by user) Phase 1.1 Phase 1.1 (Checksum:989680) REAL time: 0 secs Phase 3.3 Phase 3.3 (Checksum:1c9c37d) REAL time: 0 secs Phase 4.5 Phase 4.5 (Checksum:26259fc) REAL time: 0 secs Phase 5.8 Phase 5.8 (Checksum:2faf07b) REAL time: 0 secs Phase 6.5 Phase 6.5 (Checksum:39386fa) REAL time: 0 secs Phase 7.18 Phase 7.18 (Checksum:42c1d79) REAL time: 0 secs Writing design to file riconoscitore_1011.ncd. Total REAL time to Placer completion: 0 secs Total CPU time to Placer completion: 0 secs Phase 1: 1 unrouted; REAL time: 0 secs Phase 2: 1 unrouted; REAL time: 0 secs Phase 3: 0 unrouted; REAL time: 0 secs Phase 4: 0 unrouted; REAL time: 0 secs Total REAL time to Router completion: 0 secs Total CPU time to Router completion: 0 secs Generating "par" statistics. Generating Pad Report. All signals are completely routed. Total REAL time to PAR completion: 4 secs Total CPU time to PAR completion: 1 secs Peak Memory Usage: 55 MB Placement: Completed - No errors found. Routing: Completed - No errors found. Writing design to file riconoscitore_1011.ncd. PAR done. Completed process "Place & Route". Started process "Generate Post-Place & Route Static Timing". Analysis completed Fri Mar 16 10:28:54 2007 -------------------------------------------------------------------------------- Generating Report ... Completed process "Generate Post-Place & Route Static Timing". Place & Route Module riconoscitore_1011 . . . PAR command line: par -w -intstyle ise -ol std -t 1 riconoscitore_1011_map.ncd riconoscitore_1011.ncd riconoscitore_1011.pcf PAR completed successfully Started process "Generate Post-Place & Route Simulation Model". Completed process "Generate Post-Place & Route Simulation Model". Compiling vhdl file Z:/camurati/esercitazione_2/riconoscitore_1011.vhf in Library work. Entity (Architecture ) compiled. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file Z:/camurati/esercitazione_2/datapath.vhd in Library work. Entity (Architecture ) compiled. Compiling vhdl file Z:/camurati/esercitazione_2/next_state_logic.vhd in Library work. Architecture behavioral of Entity next_state_logic is up to date. Compiling vhdl file Z:/camurati/esercitazione_2/riconoscitore_1011.vhf in Library work. Architecture behavioral of Entity riconoscitore_1011 is up to date. ========================================================================= * HDL Analysis * ========================================================================= Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). WARNING:Xst:819 - Z:/camurati/esercitazione_2/datapath.vhd line 18: The following signals are missing in the process sensitivity list: ns. Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is Z:/camurati/esercitazione_2/next_state_logic.vhd. Found 2-bit register for signal . Summary: inferred 2 D-type flip-flop(s). Unit synthesized. Synthesizing Unit . Related source file is Z:/camurati/esercitazione_2/datapath.vhd. Found 2-bit register for signal . Found 1-bit register for signal . Summary: inferred 3 D-type flip-flop(s). Unit synthesized. Synthesizing Unit . Related source file is Z:/camurati/esercitazione_2/riconoscitore_1011.vhf. WARNING:Xst:646 - Signal is assigned but never used. WARNING:Xst:653 - Signal is used but never assigned. Tied to value 00. Unit synthesized. ========================================================================= * Advanced HDL Synthesis * ========================================================================= Advanced RAM inference ... Advanced multiplier inference ... Advanced Registered AddSub inference ... WARNING:Xst:524 - All outputs of the instance of the block are unconnected in block . This instance will be removed from the design along with all underlying logic Dynamic shift register inference ... ========================================================================= HDL Synthesis Report Macro Statistics # Registers : 2 1-bit register : 1 2-bit register : 1 ========================================================================= ========================================================================= * Low Level Synthesis * ========================================================================= WARNING:Xst:1291 - FF/Latch is unconnected in block . WARNING:Xst:1291 - FF/Latch is unconnected in block . Optimizing unit ... Optimizing unit ... Loading device for application Xst from file '3s200.nph' in environment C:/Program Files/Xilinx. Mapping all equations... WARNING:Xst:1293 - FF/Latch is constant in block . WARNING:Xst:1291 - FF/Latch is unconnected in block . WARNING:Xst:1291 - FF/Latch is unconnected in block . Building and optimizing final netlist ... Found area constraint ratio of 100 (+ 5) on block riconoscitore_1011, actual ratio is 0. ========================================================================= * Final Report * ========================================================================= Device utilization summary: --------------------------- Selected Device : 3s200ft256-4 Number of bonded IOBs: 1 out of 173 0% ========================================================================= TIMING REPORT Clock Information: ------------------ No clock signals found in this design Timing Summary: --------------- Speed Grade: -4 Minimum period: No path found Minimum input arrival time before clock: No path found Maximum output required time after clock: No path found Maximum combinational path delay: No path found ========================================================================= Completed process "Synthesize". Started process "Translate". Command Line: ngdbuild -intstyle ise -dd z:\camurati\esercitazione_2/_ngo -i -p xc3s200-ft256-4 riconoscitore_1011.ngc riconoscitore_1011.ngd Reading NGO file "Z:/camurati/esercitazione_2/riconoscitore_1011.ngc" ... Reading component libraries for design expansion... Checking timing specifications ... Checking expanded design ... NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0 Total memory usage is 38140 kilobytes Writing NGD file "riconoscitore_1011.ngd" ... Writing NGDBUILD log file "riconoscitore_1011.bld"... NGDBUILD done. Completed process "Translate". Started process "Map". Using target part "3s200ft256-4". Removing unused or disabled logic... Running cover... Running directed packing... Running delay-based LUT packing... Running related packing... Design Summary: Number of errors: 0 Number of warnings: 0 Logic Utilization: Logic Distribution: Number of Slices containing only related logic: 0 out of 0 0% Number of Slices containing unrelated logic: 0 out of 0 0% *See NOTES below for an explanation of the effects of unrelated logic Number of bonded IOBs: 1 out of 173 1% Total equivalent gate count for design: 0 Additional JTAG gate count for IOBs: 48 Peak Memory Usage: 66 MB NOTES: Related logic is defined as being logic that shares connectivity - e.g. two LUTs are "related" if they share common inputs. When assembling slices, Map gives priority to combine logic that is related. Doing so results in the best timing performance. Unrelated logic shares no connectivity. Map will only begin packing unrelated logic into a slice once 99% of the slices are occupied through related logic packing. Note that once logic distribution reaches the 99% level through related logic packing, this does not mean the device is completely utilized. Unrelated logic packing will then begin, continuing until all usable LUTs and FFs are occupied. Depending on your timing budget, increased levels of unrelated logic packing may adversely affect the overall timing performance of your design. Mapping completed. See MAP report file "riconoscitore_1011_map.mrp" for details. Completed process "Map". Mapping Module riconoscitore_1011 . . . MAP command line: map -intstyle ise -p xc3s200-ft256-4 -cm area -pr b -k 4 -c 100 -tx off -o riconoscitore_1011_map.ncd riconoscitore_1011.ngd riconoscitore_1011.pcf Mapping Module riconoscitore_1011: DONE Started process "Place & Route". Constraints file: riconoscitore_1011.pcf Loading device database for application Par from file "riconoscitore_1011_map.ncd". "riconoscitore_1011" is an NCD, version 2.38, device xc3s200, package ft256, speed -4 Loading device for application Par from file '3s200.nph' in environment C:/Program Files/Xilinx. Device speed data version: PRODUCTION 1.32 2004-06-25. Resolving physical constraints. Finished resolving physical constraints. Device utilization summary: Number of External IOBs 1 out of 173 1% Number of LOCed External IOBs 0 out of 1 0% Overall effort level (-ol): Standard (set by user) Placer effort level (-pl): Standard (set by user) Placer cost table entry (-t): 1 Router effort level (-rl): Standard (set by user) Phase 1.1 Phase 1.1 (Checksum:989680) REAL time: 0 secs Phase 3.3 Phase 3.3 (Checksum:1c9c37d) REAL time: 0 secs Phase 4.5 Phase 4.5 (Checksum:26259fc) REAL time: 0 secs Phase 5.8 Phase 5.8 (Checksum:2faf07b) REAL time: 0 secs Phase 6.5 Phase 6.5 (Checksum:39386fa) REAL time: 0 secs Phase 7.18 Phase 7.18 (Checksum:42c1d79) REAL time: 0 secs Writing design to file riconoscitore_1011.ncd. Total REAL time to Placer completion: 0 secs Total CPU time to Placer completion: 0 secs Phase 1: 1 unrouted; REAL time: 0 secs Phase 2: 1 unrouted; REAL time: 0 secs Phase 3: 0 unrouted; REAL time: 0 secs Phase 4: 0 unrouted; REAL time: 0 secs Total REAL time to Router completion: 0 secs Total CPU time to Router completion: 0 secs Generating "par" statistics. Generating Pad Report. All signals are completely routed. Total REAL time to PAR completion: 4 secs Total CPU time to PAR completion: 1 secs Peak Memory Usage: 55 MB Placement: Completed - No errors found. Routing: Completed - No errors found. Writing design to file riconoscitore_1011.ncd. PAR done. Completed process "Place & Route". Started process "Generate Post-Place & Route Static Timing". Analysis completed Fri Mar 16 10:33:06 2007 -------------------------------------------------------------------------------- Generating Report ... Completed process "Generate Post-Place & Route Static Timing". Place & Route Module riconoscitore_1011 . . . PAR command line: par -w -intstyle ise -ol std -t 1 riconoscitore_1011_map.ncd riconoscitore_1011.ncd riconoscitore_1011.pcf PAR completed successfully Started process "Generate Post-Place & Route Simulation Model". Completed process "Generate Post-Place & Route Simulation Model". Compiling vhdl file Z:/camurati/esercitazione_2/riconoscitore_1011.vhf in Library work. Entity (Architecture ) compiled. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file Z:/camurati/esercitazione_2/datapath.vhd in Library work. Entity (Architecture ) compiled. Compiling vhdl file Z:/camurati/esercitazione_2/next_state_logic.vhd in Library work. Architecture behavioral of Entity next_state_logic is up to date. Compiling vhdl file Z:/camurati/esercitazione_2/riconoscitore_1011.vhf in Library work. Architecture behavioral of Entity riconoscitore_1011 is up to date. ========================================================================= * HDL Analysis * ========================================================================= Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). WARNING:Xst:819 - Z:/camurati/esercitazione_2/datapath.vhd line 18: The following signals are missing in the process sensitivity list: ns. Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is Z:/camurati/esercitazione_2/next_state_logic.vhd. Found 2-bit register for signal . Summary: inferred 2 D-type flip-flop(s). Unit synthesized. Synthesizing Unit . Related source file is Z:/camurati/esercitazione_2/datapath.vhd. Found 2-bit register for signal . Found 1-bit register for signal . Summary: inferred 3 D-type flip-flop(s). Unit synthesized. Synthesizing Unit . Related source file is Z:/camurati/esercitazione_2/riconoscitore_1011.vhf. WARNING:Xst:646 - Signal is assigned but never used. WARNING:Xst:653 - Signal is used but never assigned. Tied to value 00. Unit synthesized. ========================================================================= * Advanced HDL Synthesis * ========================================================================= Advanced RAM inference ... Advanced multiplier inference ... Advanced Registered AddSub inference ... WARNING:Xst:524 - All outputs of the instance of the block are unconnected in block . This instance will be removed from the design along with all underlying logic Dynamic shift register inference ... ========================================================================= HDL Synthesis Report Macro Statistics # Registers : 2 1-bit register : 1 2-bit register : 1 ========================================================================= ========================================================================= * Low Level Synthesis * ========================================================================= WARNING:Xst:1291 - FF/Latch is unconnected in block . WARNING:Xst:1291 - FF/Latch is unconnected in block . Optimizing unit ... Optimizing unit ... Loading device for application Xst from file '3s200.nph' in environment C:/Program Files/Xilinx. Mapping all equations... WARNING:Xst:1293 - FF/Latch is constant in block . WARNING:Xst:1291 - FF/Latch is unconnected in block . WARNING:Xst:1291 - FF/Latch is unconnected in block . Building and optimizing final netlist ... Found area constraint ratio of 100 (+ 5) on block riconoscitore_1011, actual ratio is 0. ========================================================================= * Final Report * ========================================================================= Device utilization summary: --------------------------- Selected Device : 3s200ft256-4 Number of bonded IOBs: 1 out of 173 0% ========================================================================= TIMING REPORT Clock Information: ------------------ No clock signals found in this design Timing Summary: --------------- Speed Grade: -4 Minimum period: No path found Minimum input arrival time before clock: No path found Maximum output required time after clock: No path found Maximum combinational path delay: No path found ========================================================================= Completed process "Synthesize". Started process "Translate". Command Line: ngdbuild -intstyle ise -dd z:\camurati\esercitazione_2/_ngo -i -p xc3s200-ft256-4 riconoscitore_1011.ngc riconoscitore_1011.ngd Reading NGO file "Z:/camurati/esercitazione_2/riconoscitore_1011.ngc" ... Reading component libraries for design expansion... Checking timing specifications ... Checking expanded design ... NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0 Total memory usage is 38140 kilobytes Writing NGD file "riconoscitore_1011.ngd" ... Writing NGDBUILD log file "riconoscitore_1011.bld"... NGDBUILD done. Completed process "Translate". Started process "Map". Using target part "3s200ft256-4". Removing unused or disabled logic... Running cover... Running directed packing... Running delay-based LUT packing... Running related packing... Design Summary: Number of errors: 0 Number of warnings: 0 Logic Utilization: Logic Distribution: Number of Slices containing only related logic: 0 out of 0 0% Number of Slices containing unrelated logic: 0 out of 0 0% *See NOTES below for an explanation of the effects of unrelated logic Number of bonded IOBs: 1 out of 173 1% Total equivalent gate count for design: 0 Additional JTAG gate count for IOBs: 48 Peak Memory Usage: 66 MB NOTES: Related logic is defined as being logic that shares connectivity - e.g. two LUTs are "related" if they share common inputs. When assembling slices, Map gives priority to combine logic that is related. Doing so results in the best timing performance. Unrelated logic shares no connectivity. Map will only begin packing unrelated logic into a slice once 99% of the slices are occupied through related logic packing. Note that once logic distribution reaches the 99% level through related logic packing, this does not mean the device is completely utilized. Unrelated logic packing will then begin, continuing until all usable LUTs and FFs are occupied. Depending on your timing budget, increased levels of unrelated logic packing may adversely affect the overall timing performance of your design. Mapping completed. See MAP report file "riconoscitore_1011_map.mrp" for details. Completed process "Map". Mapping Module riconoscitore_1011 . . . MAP command line: map -intstyle ise -p xc3s200-ft256-4 -cm area -pr b -k 4 -c 100 -tx off -o riconoscitore_1011_map.ncd riconoscitore_1011.ngd riconoscitore_1011.pcf Mapping Module riconoscitore_1011: DONE Started process "Place & Route". Constraints file: riconoscitore_1011.pcf Loading device database for application Par from file "riconoscitore_1011_map.ncd". "riconoscitore_1011" is an NCD, version 2.38, device xc3s200, package ft256, speed -4 Loading device for application Par from file '3s200.nph' in environment C:/Program Files/Xilinx. Device speed data version: PRODUCTION 1.32 2004-06-25. Resolving physical constraints. Finished resolving physical constraints. Device utilization summary: Number of External IOBs 1 out of 173 1% Number of LOCed External IOBs 0 out of 1 0% Overall effort level (-ol): Standard (set by user) Placer effort level (-pl): Standard (set by user) Placer cost table entry (-t): 1 Router effort level (-rl): Standard (set by user) Phase 1.1 Phase 1.1 (Checksum:989680) REAL time: 0 secs Phase 3.3 Phase 3.3 (Checksum:1c9c37d) REAL time: 0 secs Phase 4.5 Phase 4.5 (Checksum:26259fc) REAL time: 0 secs Phase 5.8 Phase 5.8 (Checksum:2faf07b) REAL time: 0 secs Phase 6.5 Phase 6.5 (Checksum:39386fa) REAL time: 0 secs Phase 7.18 Phase 7.18 (Checksum:42c1d79) REAL time: 0 secs Writing design to file riconoscitore_1011.ncd. Total REAL time to Placer completion: 0 secs Total CPU time to Placer completion: 0 secs Phase 1: 1 unrouted; REAL time: 0 secs Phase 2: 1 unrouted; REAL time: 0 secs Phase 3: 0 unrouted; REAL time: 0 secs Phase 4: 0 unrouted; REAL time: 0 secs Total REAL time to Router completion: 0 secs Total CPU time to Router completion: 0 secs Generating "par" statistics. Generating Pad Report. All signals are completely routed. Total REAL time to PAR completion: 4 secs Total CPU time to PAR completion: 1 secs Peak Memory Usage: 55 MB Placement: Completed - No errors found. Routing: Completed - No errors found. Writing design to file riconoscitore_1011.ncd. PAR done. Completed process "Place & Route". Started process "Generate Post-Place & Route Static Timing". Analysis completed Fri Mar 16 10:36:06 2007 -------------------------------------------------------------------------------- Generating Report ... Completed process "Generate Post-Place & Route Static Timing". Place & Route Module riconoscitore_1011 . . . PAR command line: par -w -intstyle ise -ol std -t 1 riconoscitore_1011_map.ncd riconoscitore_1011.ncd riconoscitore_1011.pcf PAR completed successfully Started process "Generate Post-Place & Route Simulation Model". Completed process "Generate Post-Place & Route Simulation Model". Compiling vhdl file Z:/camurati/esercitazione_2/riconoscitore_1011.vhf in Library work. Entity (Architecture ) compiled. Project Navigator Auto-Make Log File ------------------------------------- Started process "Check Syntax". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file Z:/camurati/esercitazione_2/datapath.vhd in Library work. Entity (Architecture ) compiled. Completed process "Check Syntax". Project Navigator Auto-Make Log File ------------------------------------- Started process "Create Schematic Symbol". Compiling vhdl file Z:/camurati/esercitazione_2/datapath.vhd in Library work. Entity (Architecture ) compiled. tdtfi(vhdl) completed successfully. Release 6.3i - spl2sym G.35 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. Completed process "Create Schematic Symbol". Project Navigator Auto-Make Log File ------------------------------------- Started process "Check Syntax". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file Z:/camurati/esercitazione_2/next_state_logic.vhd in Library work. Entity (Architecture ) compiled. Completed process "Check Syntax". Project Navigator Auto-Make Log File ------------------------------------- Started process "Create Schematic Symbol". Compiling vhdl file Z:/camurati/esercitazione_2/next_state_logic.vhd in Library work. Entity (Architecture ) compiled. tdtfi(vhdl) completed successfully. Release 6.3i - spl2sym G.35 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. Completed process "Create Schematic Symbol". Project Navigator Auto-Make Log File ------------------------------------- Started process "Create Schematic Symbol". Compiling vhdl file Z:/camurati/esercitazione_2/datapath.vhd in Library work. Entity (Architecture ) compiled. tdtfi(vhdl) completed successfully. Release 6.3i - spl2sym G.35 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. Completed process "Create Schematic Symbol". Project Navigator Auto-Make Log File ------------------------------------- Started process "Create Schematic Symbol". Compiling vhdl file Z:/camurati/esercitazione_2/next_state_logic.vhd in Library work. Entity (Architecture ) compiled. tdtfi(vhdl) completed successfully. Release 6.3i - spl2sym G.35 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. Completed process "Create Schematic Symbol". Project Navigator Auto-Make Log File ------------------------------------- Started process "View VHDL Functional Model". Release 6.3i - sch2vhdl G.35 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. DRC Check completed: No Error found. Vhdl netlist file generated. Completed process "View VHDL Functional Model". Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file Z:/camurati/esercitazione_2/datapath.vhd in Library work. Architecture behavioral of Entity datapath is up to date. Compiling vhdl file Z:/camurati/esercitazione_2/next_state_logic.vhd in Library work. Architecture behavioral of Entity next_state_logic is up to date. Compiling vhdl file Z:/camurati/esercitazione_2/riconoscitore_1011.vhf in Library work. Entity (Architecture ) compiled. ========================================================================= * HDL Analysis * ========================================================================= Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). WARNING:Xst:819 - Z:/camurati/esercitazione_2/datapath.vhd line 21: The following signals are missing in the process sensitivity list: ns. Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is Z:/camurati/esercitazione_2/next_state_logic.vhd. Found 3-bit register for signal . Summary: inferred 3 D-type flip-flop(s). Unit synthesized. Synthesizing Unit . Related source file is Z:/camurati/esercitazione_2/datapath.vhd. Found 3-bit register for signal . Found 1-bit register for signal . Summary: inferred 4 D-type flip-flop(s). Unit synthesized. Synthesizing Unit . Related source file is Z:/camurati/esercitazione_2/riconoscitore_1011.vhf. Unit synthesized. ========================================================================= * Advanced HDL Synthesis * ========================================================================= Advanced RAM inference ... Advanced multiplier inference ... Advanced Registered AddSub inference ... Dynamic shift register inference ... ========================================================================= HDL Synthesis Report Macro Statistics # Registers : 3 1-bit register : 1 3-bit register : 2 ========================================================================= ========================================================================= * Low Level Synthesis * ========================================================================= Optimizing unit ... Optimizing unit ... Loading device for application Xst from file '3s200.nph' in environment C:/Program Files/Xilinx. Mapping all equations... Building and optimizing final netlist ... Found area constraint ratio of 100 (+ 5) on block riconoscitore_1011, actual ratio is 0. ========================================================================= * Final Report * ========================================================================= Device utilization summary: --------------------------- Selected Device : 3s200ft256-4 Number of Slices: 5 out of 1920 0% Number of Slice Flip Flops: 7 out of 3840 0% Number of 4 input LUTs: 8 out of 3840 0% Number of bonded IOBs: 5 out of 173 2% Number of GCLKs: 1 out of 8 12% ========================================================================= TIMING REPORT Clock Information: ------------------ -----------------------------------+------------------------+-------+ Clock Signal | Clock buffer(FF name) | Load | -----------------------------------+------------------------+-------+ Clock | BUFGP | 7 | -----------------------------------+------------------------+-------+ Timing Summary: --------------- Speed Grade: -4 Minimum period: 2.813ns (Maximum Frequency: 355.492MHz) Minimum input arrival time before clock: 3.952ns Maximum output required time after clock: 6.060ns Maximum combinational path delay: No path found ========================================================================= Completed process "Synthesize". Started process "Translate". Command Line: ngdbuild -intstyle ise -dd z:\camurati\esercitazione_2/_ngo -i -p xc3s200-ft256-4 riconoscitore_1011.ngc riconoscitore_1011.ngd Reading NGO file "Z:/camurati/esercitazione_2/riconoscitore_1011.ngc" ... Reading component libraries for design expansion... Checking timing specifications ... Checking expanded design ... NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0 Total memory usage is 38140 kilobytes Writing NGD file "riconoscitore_1011.ngd" ... Writing NGDBUILD log file "riconoscitore_1011.bld"... NGDBUILD done. Completed process "Translate". Started process "Map". Using target part "3s200ft256-4". Removing unused or disabled logic... Running cover... Running directed packing... Running delay-based LUT packing... Running related packing... Design Summary: Number of errors: 0 Number of warnings: 0 Logic Utilization: Number of Slice Flip Flops: 7 out of 3,840 1% Number of 4 input LUTs: 8 out of 3,840 1% Logic Distribution: Number of occupied Slices: 7 out of 1,920 1% Number of Slices containing only related logic: 7 out of 7 100% Number of Slices containing unrelated logic: 0 out of 7 0% *See NOTES below for an explanation of the effects of unrelated logic Total Number of 4 input LUTs: 8 out of 3,840 1% Number of bonded IOBs: 6 out of 173 3% Number of GCLKs: 1 out of 8 12% Total equivalent gate count for design: 113 Additional JTAG gate count for IOBs: 288 Peak Memory Usage: 66 MB NOTES: Related logic is defined as being logic that shares connectivity - e.g. two LUTs are "related" if they share common inputs. When assembling slices, Map gives priority to combine logic that is related. Doing so results in the best timing performance. Unrelated logic shares no connectivity. Map will only begin packing unrelated logic into a slice once 99% of the slices are occupied through related logic packing. Note that once logic distribution reaches the 99% level through related logic packing, this does not mean the device is completely utilized. Unrelated logic packing will then begin, continuing until all usable LUTs and FFs are occupied. Depending on your timing budget, increased levels of unrelated logic packing may adversely affect the overall timing performance of your design. Mapping completed. See MAP report file "riconoscitore_1011_map.mrp" for details. Completed process "Map". Mapping Module riconoscitore_1011 . . . MAP command line: map -intstyle ise -p xc3s200-ft256-4 -cm area -pr b -k 4 -c 100 -tx off -o riconoscitore_1011_map.ncd riconoscitore_1011.ngd riconoscitore_1011.pcf Mapping Module riconoscitore_1011: DONE Started process "Place & Route". Constraints file: riconoscitore_1011.pcf Loading device database for application Par from file "riconoscitore_1011_map.ncd". "riconoscitore_1011" is an NCD, version 2.38, device xc3s200, package ft256, speed -4 Loading device for application Par from file '3s200.nph' in environment C:/Program Files/Xilinx. Device speed data version: PRODUCTION 1.32 2004-06-25. Resolving physical constraints. Finished resolving physical constraints. Device utilization summary: Number of External IOBs 6 out of 173 3% Number of LOCed External IOBs 0 out of 6 0% Number of Slices 7 out of 1920 1% Number of BUFGMUXs 1 out of 8 12% Overall effort level (-ol): Standard (set by user) Placer effort level (-pl): Standard (set by user) Placer cost table entry (-t): 1 Router effort level (-rl): Standard (set by user) Phase 1.1 Phase 1.1 (Checksum:9896a9) REAL time: 0 secs . Phase 3.3 Phase 3.3 (Checksum:1c9c37d) REAL time: 0 secs Phase 4.5 Phase 4.5 (Checksum:26259fc) REAL time: 0 secs Phase 5.8 . Phase 5.8 (Checksum:98d243) REAL time: 0 secs Phase 6.5 Phase 6.5 (Checksum:39386fa) REAL time: 0 secs Phase 7.18 Phase 7.18 (Checksum:42c1d79) REAL time: 0 secs Writing design to file riconoscitore_1011.ncd. Total REAL time to Placer completion: 0 secs Total CPU time to Placer completion: 0 secs Phase 1: 50 unrouted; REAL time: 0 secs Phase 2: 43 unrouted; REAL time: 0 secs Phase 3: 9 unrouted; REAL time: 0 secs Phase 4: 0 unrouted; REAL time: 0 secs Total REAL time to Router completion: 0 secs Total CPU time to Router completion: 0 secs Generating "par" statistics. ************************** Generating Clock Report ************************** +-------------------------+----------+------+------+------------+-------------+ | Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)| +-------------------------+----------+------+------+------------+-------------+ | Clock_BUFGP | BUFGMUX3| No | 6 | 0.000 | 1.012 | +-------------------------+----------+------+------+------------+-------------+ Generating Pad Report. All signals are completely routed. Total REAL time to PAR completion: 4 secs Total CPU time to PAR completion: 1 secs Peak Memory Usage: 56 MB Placement: Completed - No errors found. Routing: Completed - No errors found. Writing design to file riconoscitore_1011.ncd. PAR done. Completed process "Place & Route". Started process "Generate Post-Place & Route Static Timing". Analysis completed Fri Mar 16 10:48:16 2007 -------------------------------------------------------------------------------- Generating Report ... Completed process "Generate Post-Place & Route Static Timing". Place & Route Module riconoscitore_1011 . . . PAR command line: par -w -intstyle ise -ol std -t 1 riconoscitore_1011_map.ncd riconoscitore_1011.ncd riconoscitore_1011.pcf PAR completed successfully Started process "Generate Post-Place & Route Simulation Model". Completed process "Generate Post-Place & Route Simulation Model". Compiling vhdl file Z:/camurati/esercitazione_2/riconoscitore_1011.vhf in Library work. Entity (Architecture ) compiled. Project Navigator Auto-Make Log File ------------------------------------- Compiling vhdl file Z:/camurati/esercitazione_2/riconoscitore_1011.vhf in Library work. Entity (Architecture ) compiled. Project Navigator Auto-Make Log File ------------------------------------- Started process "View VHDL Functional Model". Release 6.3i - sch2vhdl G.35 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. DRC Check completed: No Error found. Vhdl netlist file generated. Completed process "View VHDL Functional Model". Project Navigator Auto-Make Log File ------------------------------------- Started process "View VHDL Functional Model". Release 6.3i - sch2vhdl G.35 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. DRC Check completed: No Error found. Vhdl netlist file generated. Completed process "View VHDL Functional Model". Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file Z:/camurati/esercitazione_2/datapath.vhd in Library work. Architecture behavioral of Entity datapath is up to date. Compiling vhdl file Z:/camurati/esercitazione_2/next_state_logic.vhd in Library work. Architecture behavioral of Entity next_state_logic is up to date. Compiling vhdl file Z:/camurati/esercitazione_2/riconoscitore_1011.vhf in Library work. Entity (Architecture ) compiled. ========================================================================= * HDL Analysis * ========================================================================= Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). WARNING:Xst:819 - Z:/camurati/esercitazione_2/datapath.vhd line 21: The following signals are missing in the process sensitivity list: ns. Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is Z:/camurati/esercitazione_2/next_state_logic.vhd. Found 3-bit register for signal . Summary: inferred 3 D-type flip-flop(s). Unit synthesized. Synthesizing Unit . Related source file is Z:/camurati/esercitazione_2/datapath.vhd. Found 3-bit register for signal . Found 1-bit register for signal . Summary: inferred 4 D-type flip-flop(s). Unit synthesized. Synthesizing Unit . Related source file is Z:/camurati/esercitazione_2/riconoscitore_1011.vhf. Unit synthesized. ========================================================================= * Advanced HDL Synthesis * ========================================================================= Advanced RAM inference ... Advanced multiplier inference ... Advanced Registered AddSub inference ... Dynamic shift register inference ... ========================================================================= HDL Synthesis Report Macro Statistics # Registers : 3 1-bit register : 1 3-bit register : 2 ========================================================================= ========================================================================= * Low Level Synthesis * ========================================================================= Optimizing unit ... Optimizing unit ... Loading device for application Xst from file '3s200.nph' in environment C:/Program Files/Xilinx. Mapping all equations... Building and optimizing final netlist ... Found area constraint ratio of 100 (+ 5) on block riconoscitore_1011, actual ratio is 0. ========================================================================= * Final Report * ========================================================================= Device utilization summary: --------------------------- Selected Device : 3s200ft256-4 Number of Slices: 5 out of 1920 0% Number of Slice Flip Flops: 7 out of 3840 0% Number of 4 input LUTs: 8 out of 3840 0% Number of bonded IOBs: 8 out of 173 4% Number of GCLKs: 1 out of 8 12% ========================================================================= TIMING REPORT Clock Information: ------------------ -----------------------------------+------------------------+-------+ Clock Signal | Clock buffer(FF name) | Load | -----------------------------------+------------------------+-------+ Clock | BUFGP | 7 | -----------------------------------+------------------------+-------+ Timing Summary: --------------- Speed Grade: -4 Minimum period: 2.842ns (Maximum Frequency: 351.865MHz) Minimum input arrival time before clock: 3.952ns Maximum output required time after clock: 6.312ns Maximum combinational path delay: No path found ========================================================================= Completed process "Synthesize". Started process "Translate". Command Line: ngdbuild -intstyle ise -dd z:\camurati\esercitazione_2/_ngo -i -p xc3s200-ft256-4 riconoscitore_1011.ngc riconoscitore_1011.ngd Reading NGO file "Z:/camurati/esercitazione_2/riconoscitore_1011.ngc" ... Reading component libraries for design expansion... Checking timing specifications ... Checking expanded design ... NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0 Total memory usage is 38140 kilobytes Writing NGD file "riconoscitore_1011.ngd" ... Writing NGDBUILD log file "riconoscitore_1011.bld"... NGDBUILD done. Completed process "Translate". Started process "Map". Using target part "3s200ft256-4". Removing unused or disabled logic... Running cover... Running directed packing... Running delay-based LUT packing... Running related packing... Design Summary: Number of errors: 0 Number of warnings: 0 Logic Utilization: Number of Slice Flip Flops: 7 out of 3,840 1% Number of 4 input LUTs: 8 out of 3,840 1% Logic Distribution: Number of occupied Slices: 7 out of 1,920 1% Number of Slices containing only related logic: 7 out of 7 100% Number of Slices containing unrelated logic: 0 out of 7 0% *See NOTES below for an explanation of the effects of unrelated logic Total Number of 4 input LUTs: 8 out of 3,840 1% Number of bonded IOBs: 9 out of 173 5% Number of GCLKs: 1 out of 8 12% Total equivalent gate count for design: 113 Additional JTAG gate count for IOBs: 432 Peak Memory Usage: 66 MB NOTES: Related logic is defined as being logic that shares connectivity - e.g. two LUTs are "related" if they share common inputs. When assembling slices, Map gives priority to combine logic that is related. Doing so results in the best timing performance. Unrelated logic shares no connectivity. Map will only begin packing unrelated logic into a slice once 99% of the slices are occupied through related logic packing. Note that once logic distribution reaches the 99% level through related logic packing, this does not mean the device is completely utilized. Unrelated logic packing will then begin, continuing until all usable LUTs and FFs are occupied. Depending on your timing budget, increased levels of unrelated logic packing may adversely affect the overall timing performance of your design. Mapping completed. See MAP report file "riconoscitore_1011_map.mrp" for details. Completed process "Map". Mapping Module riconoscitore_1011 . . . MAP command line: map -intstyle ise -p xc3s200-ft256-4 -cm area -pr b -k 4 -c 100 -tx off -o riconoscitore_1011_map.ncd riconoscitore_1011.ngd riconoscitore_1011.pcf Mapping Module riconoscitore_1011: DONE Started process "Place & Route". Constraints file: riconoscitore_1011.pcf Loading device database for application Par from file "riconoscitore_1011_map.ncd". "riconoscitore_1011" is an NCD, version 2.38, device xc3s200, package ft256, speed -4 Loading device for application Par from file '3s200.nph' in environment C:/Program Files/Xilinx. Device speed data version: PRODUCTION 1.32 2004-06-25. Resolving physical constraints. Finished resolving physical constraints. Device utilization summary: Number of External IOBs 9 out of 173 5% Number of LOCed External IOBs 0 out of 9 0% Number of Slices 7 out of 1920 1% Number of BUFGMUXs 1 out of 8 12% Overall effort level (-ol): Standard (set by user) Placer effort level (-pl): Standard (set by user) Placer cost table entry (-t): 1 Router effort level (-rl): Standard (set by user) Phase 1.1 Phase 1.1 (Checksum:9896b2) REAL time: 0 secs . Phase 3.3 Phase 3.3 (Checksum:1c9c37d) REAL time: 0 secs Phase 4.5 Phase 4.5 (Checksum:26259fc) REAL time: 0 secs Phase 5.8 . Phase 5.8 (Checksum:98d94b) REAL time: 0 secs Phase 6.5 Phase 6.5 (Checksum:39386fa) REAL time: 0 secs Phase 7.18 Phase 7.18 (Checksum:42c1d79) REAL time: 0 secs Writing design to file riconoscitore_1011.ncd. Total REAL time to Placer completion: 0 secs Total CPU time to Placer completion: 0 secs Phase 1: 53 unrouted; REAL time: 0 secs Phase 2: 46 unrouted; REAL time: 0 secs Phase 3: 12 unrouted; REAL time: 0 secs Phase 4: 0 unrouted; REAL time: 0 secs Total REAL time to Router completion: 0 secs Total CPU time to Router completion: 0 secs Generating "par" statistics. ************************** Generating Clock Report ************************** +-------------------------+----------+------+------+------------+-------------+ | Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)| +-------------------------+----------+------+------+------------+-------------+ | Clock_BUFGP | BUFGMUX3| No | 6 | 0.000 | 1.011 | +-------------------------+----------+------+------+------------+-------------+ Generating Pad Report. All signals are completely routed. Total REAL time to PAR completion: 4 secs Total CPU time to PAR completion: 1 secs Peak Memory Usage: 56 MB Placement: Completed - No errors found. Routing: Completed - No errors found. Writing design to file riconoscitore_1011.ncd. PAR done. Completed process "Place & Route". Started process "Generate Post-Place & Route Static Timing". Analysis completed Fri Mar 16 10:52:16 2007 -------------------------------------------------------------------------------- Generating Report ... Completed process "Generate Post-Place & Route Static Timing". Place & Route Module riconoscitore_1011 . . . PAR command line: par -w -intstyle ise -ol std -t 1 riconoscitore_1011_map.ncd riconoscitore_1011.ncd riconoscitore_1011.pcf PAR completed successfully Started process "Generate Post-Place & Route Simulation Model". Completed process "Generate Post-Place & Route Simulation Model". Compiling vhdl file Z:/camurati/esercitazione_2/riconoscitore_1011.vhf in Library work. Entity (Architecture ) compiled. Project Navigator Auto-Make Log File ------------------------------------- Started process "View VHDL Functional Model". Release 6.3i - sch2vhdl G.35 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. DRC Check completed: No Error found. Vhdl netlist file generated. Completed process "View VHDL Functional Model". Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file Z:/camurati/esercitazione_2/datapath.vhd in Library work. Architecture behavioral of Entity datapath is up to date. Compiling vhdl file Z:/camurati/esercitazione_2/next_state_logic.vhd in Library work. Architecture behavioral of Entity next_state_logic is up to date. Compiling vhdl file Z:/camurati/esercitazione_2/riconoscitore_1011.vhf in Library work. Architecture behavioral of Entity riconoscitore_1011 is up to date. ========================================================================= * HDL Analysis * ========================================================================= Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). WARNING:Xst:819 - Z:/camurati/esercitazione_2/datapath.vhd line 21: The following signals are missing in the process sensitivity list: ns. Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is Z:/camurati/esercitazione_2/next_state_logic.vhd. Found 3-bit register for signal . Summary: inferred 3 D-type flip-flop(s). Unit synthesized. Synthesizing Unit . Related source file is Z:/camurati/esercitazione_2/datapath.vhd. Found 3-bit register for signal . Found 1-bit register for signal . Summary: inferred 4 D-type flip-flop(s). Unit synthesized. Synthesizing Unit . Related source file is Z:/camurati/esercitazione_2/riconoscitore_1011.vhf. Unit synthesized. ========================================================================= * Advanced HDL Synthesis * ========================================================================= Advanced RAM inference ... Advanced multiplier inference ... Advanced Registered AddSub inference ... Dynamic shift register inference ... ========================================================================= HDL Synthesis Report Macro Statistics # Registers : 3 1-bit register : 1 3-bit register : 2 ========================================================================= ========================================================================= * Low Level Synthesis * ========================================================================= Optimizing unit ... Optimizing unit ... Loading device for application Xst from file '3s200.nph' in environment C:/Program Files/Xilinx. Mapping all equations... Building and optimizing final netlist ... Found area constraint ratio of 100 (+ 5) on block riconoscitore_1011, actual ratio is 0. ========================================================================= * Final Report * ========================================================================= Device utilization summary: --------------------------- Selected Device : 3s200ft256-4 Number of Slices: 5 out of 1920 0% Number of Slice Flip Flops: 7 out of 3840 0% Number of 4 input LUTs: 8 out of 3840 0% Number of bonded IOBs: 7 out of 173 4% Number of GCLKs: 1 out of 8 12% ========================================================================= TIMING REPORT Clock Information: ------------------ -----------------------------------+------------------------+-------+ Clock Signal | Clock buffer(FF name) | Load | -----------------------------------+------------------------+-------+ Clock | BUFGP | 7 | -----------------------------------+------------------------+-------+ Timing Summary: --------------- Speed Grade: -4 Minimum period: 2.842ns (Maximum Frequency: 351.865MHz) Minimum input arrival time before clock: 4.040ns Maximum output required time after clock: 6.312ns Maximum combinational path delay: No path found ========================================================================= Completed process "Synthesize". Started process "Translate". Command Line: ngdbuild -intstyle ise -dd z:\camurati\esercitazione_2/_ngo -i -p xc3s200-ft256-4 riconoscitore_1011.ngc riconoscitore_1011.ngd Reading NGO file "Z:/camurati/esercitazione_2/riconoscitore_1011.ngc" ... Reading component libraries for design expansion... Checking timing specifications ... Checking expanded design ... NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0 Total memory usage is 38140 kilobytes Writing NGD file "riconoscitore_1011.ngd" ... Writing NGDBUILD log file "riconoscitore_1011.bld"... NGDBUILD done. Completed process "Translate". Started process "Map". Using target part "3s200ft256-4". Removing unused or disabled logic... Running cover... Running directed packing... Running delay-based LUT packing... Running related packing... Design Summary: Number of errors: 0 Number of warnings: 0 Logic Utilization: Number of Slice Flip Flops: 7 out of 3,840 1% Number of 4 input LUTs: 8 out of 3,840 1% Logic Distribution: Number of occupied Slices: 7 out of 1,920 1% Number of Slices containing only related logic: 7 out of 7 100% Number of Slices containing unrelated logic: 0 out of 7 0% *See NOTES below for an explanation of the effects of unrelated logic Total Number of 4 input LUTs: 8 out of 3,840 1% Number of bonded IOBs: 8 out of 173 4% Number of GCLKs: 1 out of 8 12% Total equivalent gate count for design: 113 Additional JTAG gate count for IOBs: 384 Peak Memory Usage: 66 MB NOTES: Related logic is defined as being logic that shares connectivity - e.g. two LUTs are "related" if they share common inputs. When assembling slices, Map gives priority to combine logic that is related. Doing so results in the best timing performance. Unrelated logic shares no connectivity. Map will only begin packing unrelated logic into a slice once 99% of the slices are occupied through related logic packing. Note that once logic distribution reaches the 99% level through related logic packing, this does not mean the device is completely utilized. Unrelated logic packing will then begin, continuing until all usable LUTs and FFs are occupied. Depending on your timing budget, increased levels of unrelated logic packing may adversely affect the overall timing performance of your design. Mapping completed. See MAP report file "riconoscitore_1011_map.mrp" for details. Completed process "Map". Mapping Module riconoscitore_1011 . . . MAP command line: map -intstyle ise -p xc3s200-ft256-4 -cm area -pr b -k 4 -c 100 -tx off -o riconoscitore_1011_map.ncd riconoscitore_1011.ngd riconoscitore_1011.pcf Mapping Module riconoscitore_1011: DONE Started process "Place & Route". Constraints file: riconoscitore_1011.pcf Loading device database for application Par from file "riconoscitore_1011_map.ncd". "riconoscitore_1011" is an NCD, version 2.38, device xc3s200, package ft256, speed -4 Loading device for application Par from file '3s200.nph' in environment C:/Program Files/Xilinx. Device speed data version: PRODUCTION 1.32 2004-06-25. Resolving physical constraints. Finished resolving physical constraints. Device utilization summary: Number of External IOBs 8 out of 173 4% Number of LOCed External IOBs 0 out of 8 0% Number of Slices 7 out of 1920 1% Number of BUFGMUXs 1 out of 8 12% Overall effort level (-ol): Standard (set by user) Placer effort level (-pl): Standard (set by user) Placer cost table entry (-t): 1 Router effort level (-rl): Standard (set by user) Phase 1.1 Phase 1.1 (Checksum:9896af) REAL time: 0 secs . Phase 3.3 Phase 3.3 (Checksum:1c9c37d) REAL time: 0 secs Phase 4.5 Phase 4.5 (Checksum:26259fc) REAL time: 0 secs Phase 5.8 . Phase 5.8 (Checksum:98ce29) REAL time: 0 secs Phase 6.5 Phase 6.5 (Checksum:39386fa) REAL time: 0 secs Phase 7.18 Phase 7.18 (Checksum:42c1d79) REAL time: 0 secs Writing design to file riconoscitore_1011.ncd. Total REAL time to Placer completion: 0 secs Total CPU time to Placer completion: 0 secs Phase 1: 53 unrouted; REAL time: 0 secs Phase 2: 46 unrouted; REAL time: 0 secs Phase 3: 15 unrouted; REAL time: 0 secs Phase 4: 0 unrouted; REAL time: 0 secs Total REAL time to Router completion: 0 secs Total CPU time to Router completion: 0 secs Generating "par" statistics. ************************** Generating Clock Report ************************** +-------------------------+----------+------+------+------------+-------------+ | Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)| +-------------------------+----------+------+------+------------+-------------+ | Clock_BUFGP | BUFGMUX0| No | 6 | 0.000 | 1.011 | +-------------------------+----------+------+------+------------+-------------+ Generating Pad Report. All signals are completely routed. Total REAL time to PAR completion: 4 secs Total CPU time to PAR completion: 1 secs Peak Memory Usage: 56 MB Placement: Completed - No errors found. Routing: Completed - No errors found. Writing design to file riconoscitore_1011.ncd. PAR done. Completed process "Place & Route". Started process "Generate Post-Place & Route Static Timing". Analysis completed Fri Mar 16 10:56:59 2007 -------------------------------------------------------------------------------- Generating Report ... Completed process "Generate Post-Place & Route Static Timing". Place & Route Module riconoscitore_1011 . . . PAR command line: par -w -intstyle ise -ol std -t 1 riconoscitore_1011_map.ncd riconoscitore_1011.ncd riconoscitore_1011.pcf PAR completed successfully Started process "Generate Post-Place & Route Simulation Model". Completed process "Generate Post-Place & Route Simulation Model". Compiling vhdl file Z:/camurati/esercitazione_2/riconoscitore_1011.vhf in Library work. Entity (Architecture ) compiled. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file Z:/camurati/esercitazione_2/datapath.vhd in Library work. ERROR:HDLParsers:410 - Z:/camurati/esercitazione_2/datapath.vhd Line 27. Variable 'ns' ns is at left hand side of signal assignment statement. ERROR:HDLParsers:410 - Z:/camurati/esercitazione_2/datapath.vhd Line 33. Variable 'ns' ns is at left hand side of signal assignment statement. ERROR:HDLParsers:410 - Z:/camurati/esercitazione_2/datapath.vhd Line 40. Variable 'ns' ns is at left hand side of signal assignment statement. ERROR:HDLParsers:410 - Z:/camurati/esercitazione_2/datapath.vhd Line 47. Variable 'ns' ns is at left hand side of signal assignment statement. ERROR:HDLParsers:410 - Z:/camurati/esercitazione_2/datapath.vhd Line 49. Variable 'ns' ns is at left hand side of signal assignment statement. ERROR:HDLParsers:410 - Z:/camurati/esercitazione_2/datapath.vhd Line 54. Variable 'ns' ns is at left hand side of signal assignment statement. ERROR:HDLParsers:410 - Z:/camurati/esercitazione_2/datapath.vhd Line 56. Variable 'ns' ns is at left hand side of signal assignment statement. ERROR:HDLParsers:410 - Z:/camurati/esercitazione_2/datapath.vhd Line 61. Variable 'ns' ns is at left hand side of signal assignment statement. ERROR:HDLParsers:410 - Z:/camurati/esercitazione_2/datapath.vhd Line 63. Variable 'ns' ns is at left hand side of signal assignment statement. --> Total memory usage is 47344 kilobytes ERROR: XST failed Process "Synthesize" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Check Syntax". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file Z:/camurati/esercitazione_2/datapath.vhd in Library work. ERROR:HDLParsers:3014 - Z:/camurati/esercitazione_2/datapath.vhd Line 4. Library unit STD_LOGIC_UnstateIGNED is not available in library IEEE. ERROR: XST failed Process "Check Syntax" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Check Syntax". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file Z:/camurati/esercitazione_2/datapath.vhd in Library work. ERROR:HDLParsers:410 - Z:/camurati/esercitazione_2/datapath.vhd Line 28. Variable 'nstate' nstate is at left hand side of signal assignment statement. ERROR:HDLParsers:410 - Z:/camurati/esercitazione_2/datapath.vhd Line 32. Variable 'u' u is at left hand side of signal assignment statement. ERROR:HDLParsers:410 - Z:/camurati/esercitazione_2/datapath.vhd Line 34. Variable 'nstate' nstate is at left hand side of signal assignment statement. ERROR:HDLParsers:410 - Z:/camurati/esercitazione_2/datapath.vhd Line 39. Variable 'u' u is at left hand side of signal assignment statement. ERROR:HDLParsers:410 - Z:/camurati/esercitazione_2/datapath.vhd Line 41. Variable 'nstate' nstate is at left hand side of signal assignment statement. ERROR:HDLParsers:410 - Z:/camurati/esercitazione_2/datapath.vhd Line 46. Variable 'u' u is at left hand side of signal assignment statement. ERROR:HDLParsers:410 - Z:/camurati/esercitazione_2/datapath.vhd Line 48. Variable 'nstate' nstate is at left hand side of signal assignment statement. ERROR:HDLParsers:410 - Z:/camurati/esercitazione_2/datapath.vhd Line 50. Variable 'nstate' nstate is at left hand side of signal assignment statement. ERROR:HDLParsers:410 - Z:/camurati/esercitazione_2/datapath.vhd Line 53. Variable 'u' u is at left hand side of signal assignment statement. ERROR:HDLParsers:410 - Z:/camurati/esercitazione_2/datapath.vhd Line 55. Variable 'nstate' nstate is at left hand side of signal assignment statement. ERROR:HDLParsers:410 - Z:/camurati/esercitazione_2/datapath.vhd Line 57. Variable 'nstate' nstate is at left hand side of signal assignment statement. ERROR:HDLParsers:410 - Z:/camurati/esercitazione_2/datapath.vhd Line 60. Variable 'u' u is at left hand side of signal assignment statement. ERROR:HDLParsers:410 - Z:/camurati/esercitazione_2/datapath.vhd Line 62. Variable 'nstate' nstate is at left hand side of signal assignment statement. ERROR:HDLParsers:410 - Z:/camurati/esercitazione_2/datapath.vhd Line 64. Variable 'nstate' nstate is at left hand side of signal assignment statement. ERROR:HDLParsers:3312 - Z:/camurati/esercitazione_2/datapath.vhd Line 72. Undefined symbol 'u'. ERROR:HDLParsers:1209 - Z:/camurati/esercitazione_2/datapath.vhd Line 72. u: Undefined symbol (last report in this block) ERROR: XST failed Process "Check Syntax" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Check Syntax". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file Z:/camurati/esercitazione_2/datapath.vhd in Library work. ERROR:HDLParsers:410 - Z:/camurati/esercitazione_2/datapath.vhd Line 53. Variable 'u' u is at left hand side of signal assignment statement. ERROR:HDLParsers:410 - Z:/camurati/esercitazione_2/datapath.vhd Line 60. Variable 'u' u is at left hand side of signal assignment statement. ERROR:HDLParsers:3312 - Z:/camurati/esercitazione_2/datapath.vhd Line 72. Undefined symbol 'u'. ERROR:HDLParsers:1209 - Z:/camurati/esercitazione_2/datapath.vhd Line 72. u: Undefined symbol (last report in this block) ERROR: XST failed Process "Check Syntax" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Check Syntax". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file Z:/camurati/esercitazione_2/datapath.vhd in Library work. Entity (Architecture ) compiled. Completed process "Check Syntax". Project Navigator Auto-Make Log File ------------------------------------- Started process "View VHDL Functional Model". Release 6.3i - sch2vhdl G.35 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. DRC Check completed: No Error found. Vhdl netlist file generated. Completed process "View VHDL Functional Model". Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file Z:/camurati/esercitazione_2/datapath.vhd in Library work. Architecture behavioral of Entity datapath is up to date. Compiling vhdl file Z:/camurati/esercitazione_2/next_state_logic.vhd in Library work. Architecture behavioral of Entity next_state_logic is up to date. Compiling vhdl file Z:/camurati/esercitazione_2/riconoscitore_1011.vhf in Library work. Entity (Architecture ) compiled. ========================================================================= * HDL Analysis * ========================================================================= Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is Z:/camurati/esercitazione_2/next_state_logic.vhd. Found 3-bit register for signal . Summary: inferred 3 D-type flip-flop(s). Unit synthesized. Synthesizing Unit . Related source file is Z:/camurati/esercitazione_2/datapath.vhd. Found 3-bit register for signal . Found 1-bit register for signal . Summary: inferred 4 D-type flip-flop(s). Unit synthesized. Synthesizing Unit . Related source file is Z:/camurati/esercitazione_2/riconoscitore_1011.vhf. Unit synthesized. ========================================================================= * Advanced HDL Synthesis * ========================================================================= Advanced RAM inference ... Advanced multiplier inference ... Advanced Registered AddSub inference ... Dynamic shift register inference ... ========================================================================= HDL Synthesis Report Macro Statistics # Registers : 3 1-bit register : 1 3-bit register : 2 ========================================================================= ========================================================================= * Low Level Synthesis * ========================================================================= Optimizing unit ... Optimizing unit ... Loading device for application Xst from file '3s200.nph' in environment C:/Program Files/Xilinx. Mapping all equations... Building and optimizing final netlist ... Found area constraint ratio of 100 (+ 5) on block riconoscitore_1011, actual ratio is 0. ========================================================================= * Final Report * ========================================================================= Device utilization summary: --------------------------- Selected Device : 3s200ft256-4 Number of Slices: 5 out of 1920 0% Number of Slice Flip Flops: 7 out of 3840 0% Number of 4 input LUTs: 8 out of 3840 0% Number of bonded IOBs: 7 out of 173 4% Number of GCLKs: 1 out of 8 12% ========================================================================= TIMING REPORT Clock Information: ------------------ -----------------------------------+------------------------+-------+ Clock Signal | Clock buffer(FF name) | Load | -----------------------------------+------------------------+-------+ Clock | BUFGP | 7 | -----------------------------------+------------------------+-------+ Timing Summary: --------------- Speed Grade: -4 Minimum period: 2.581ns (Maximum Frequency: 387.447MHz) Minimum input arrival time before clock: 4.040ns Maximum output required time after clock: 6.342ns Maximum combinational path delay: No path found ========================================================================= Completed process "Synthesize". Started process "Translate". Command Line: ngdbuild -intstyle ise -dd z:\camurati\esercitazione_2/_ngo -i -p xc3s200-ft256-4 riconoscitore_1011.ngc riconoscitore_1011.ngd Reading NGO file "Z:/camurati/esercitazione_2/riconoscitore_1011.ngc" ... Reading component libraries for design expansion... Checking timing specifications ... Checking expanded design ... NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0 Total memory usage is 38140 kilobytes Writing NGD file "riconoscitore_1011.ngd" ... Writing NGDBUILD log file "riconoscitore_1011.bld"... NGDBUILD done. Completed process "Translate". Started process "Map". Using target part "3s200ft256-4". Removing unused or disabled logic... Running cover... Running directed packing... Running delay-based LUT packing... Running related packing... Design Summary: Number of errors: 0 Number of warnings: 0 Logic Utilization: Number of Slice Flip Flops: 7 out of 3,840 1% Number of 4 input LUTs: 8 out of 3,840 1% Logic Distribution: Number of occupied Slices: 7 out of 1,920 1% Number of Slices containing only related logic: 7 out of 7 100% Number of Slices containing unrelated logic: 0 out of 7 0% *See NOTES below for an explanation of the effects of unrelated logic Total Number of 4 input LUTs: 8 out of 3,840 1% Number of bonded IOBs: 8 out of 173 4% Number of GCLKs: 1 out of 8 12% Total equivalent gate count for design: 116 Additional JTAG gate count for IOBs: 384 Peak Memory Usage: 66 MB NOTES: Related logic is defined as being logic that shares connectivity - e.g. two LUTs are "related" if they share common inputs. When assembling slices, Map gives priority to combine logic that is related. Doing so results in the best timing performance. Unrelated logic shares no connectivity. Map will only begin packing unrelated logic into a slice once 99% of the slices are occupied through related logic packing. Note that once logic distribution reaches the 99% level through related logic packing, this does not mean the device is completely utilized. Unrelated logic packing will then begin, continuing until all usable LUTs and FFs are occupied. Depending on your timing budget, increased levels of unrelated logic packing may adversely affect the overall timing performance of your design. Mapping completed. See MAP report file "riconoscitore_1011_map.mrp" for details. Completed process "Map". Mapping Module riconoscitore_1011 . . . MAP command line: map -intstyle ise -p xc3s200-ft256-4 -cm area -pr b -k 4 -c 100 -tx off -o riconoscitore_1011_map.ncd riconoscitore_1011.ngd riconoscitore_1011.pcf Mapping Module riconoscitore_1011: DONE Started process "Place & Route". Constraints file: riconoscitore_1011.pcf Loading device database for application Par from file "riconoscitore_1011_map.ncd". "riconoscitore_1011" is an NCD, version 2.38, device xc3s200, package ft256, speed -4 Loading device for application Par from file '3s200.nph' in environment C:/Program Files/Xilinx. Device speed data version: PRODUCTION 1.32 2004-06-25. Resolving physical constraints. Finished resolving physical constraints. Device utilization summary: Number of External IOBs 8 out of 173 4% Number of LOCed External IOBs 0 out of 8 0% Number of Slices 7 out of 1920 1% Number of BUFGMUXs 1 out of 8 12% Overall effort level (-ol): Standard (set by user) Placer effort level (-pl): Standard (set by user) Placer cost table entry (-t): 1 Router effort level (-rl): Standard (set by user) Phase 1.1 Phase 1.1 (Checksum:9896af) REAL time: 0 secs . Phase 3.3 Phase 3.3 (Checksum:1c9c37d) REAL time: 0 secs Phase 4.5 Phase 4.5 (Checksum:26259fc) REAL time: 0 secs Phase 5.8 . Phase 5.8 (Checksum:98caf0) REAL time: 0 secs Phase 6.5 Phase 6.5 (Checksum:39386fa) REAL time: 0 secs Phase 7.18 Phase 7.18 (Checksum:42c1d79) REAL time: 0 secs Writing design to file riconoscitore_1011.ncd. Total REAL time to Placer completion: 0 secs Total CPU time to Placer completion: 0 secs Phase 1: 57 unrouted; REAL time: 0 secs Phase 2: 50 unrouted; REAL time: 0 secs Phase 3: 26 unrouted; REAL time: 0 secs Phase 4: 0 unrouted; REAL time: 0 secs Total REAL time to Router completion: 0 secs Total CPU time to Router completion: 0 secs Generating "par" statistics. ************************** Generating Clock Report ************************** +-------------------------+----------+------+------+------------+-------------+ | Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)| +-------------------------+----------+------+------+------------+-------------+ | Clock_BUFGP | BUFGMUX0| No | 6 | 0.000 | 1.011 | +-------------------------+----------+------+------+------------+-------------+ Generating Pad Report. All signals are completely routed. Total REAL time to PAR completion: 4 secs Total CPU time to PAR completion: 1 secs Peak Memory Usage: 56 MB Placement: Completed - No errors found. Routing: Completed - No errors found. Writing design to file riconoscitore_1011.ncd. PAR done. Completed process "Place & Route". Started process "Generate Post-Place & Route Static Timing". Analysis completed Fri Mar 16 11:03:48 2007 -------------------------------------------------------------------------------- Generating Report ... Completed process "Generate Post-Place & Route Static Timing". Place & Route Module riconoscitore_1011 . . . PAR command line: par -w -intstyle ise -ol std -t 1 riconoscitore_1011_map.ncd riconoscitore_1011.ncd riconoscitore_1011.pcf PAR completed successfully Started process "Generate Post-Place & Route Simulation Model". Completed process "Generate Post-Place & Route Simulation Model". Compiling vhdl file Z:/camurati/esercitazione_2/riconoscitore_1011.vhf in Library work. Entity (Architecture ) compiled. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file Z:/camurati/esercitazione_2/datapath.vhd in Library work. Architecture behavioral of Entity datapath is up to date. ========================================================================= * HDL Analysis * ========================================================================= Analyzing Entity (Architecture ). Entity analyzed. Unit generated. ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is Z:/camurati/esercitazione_2/datapath.vhd. Found 3-bit register for signal . Found 1-bit register for signal . Summary: inferred 4 D-type flip-flop(s). Unit synthesized. ========================================================================= * Advanced HDL Synthesis * ========================================================================= Advanced RAM inference ... Advanced multiplier inference ... Advanced Registered AddSub inference ... Dynamic shift register inference ... ========================================================================= HDL Synthesis Report Macro Statistics # Registers : 2 1-bit register : 1 3-bit register : 1 ========================================================================= ========================================================================= * Low Level Synthesis * ========================================================================= Optimizing unit ... Loading device for application Xst from file '3s200.nph' in environment C:/Program Files/Xilinx. Mapping all equations... Building and optimizing final netlist ... Found area constraint ratio of 100 (+ 5) on block datapath, actual ratio is 0. ========================================================================= * Final Report * ========================================================================= Device utilization summary: --------------------------- Selected Device : 3s200ft256-4 Number of Slices: 5 out of 1920 0% Number of Slice Flip Flops: 4 out of 3840 0% Number of 4 input LUTs: 10 out of 3840 0% Number of bonded IOBs: 10 out of 173 5% Number of GCLKs: 1 out of 8 12% ========================================================================= TIMING REPORT Clock Information: ------------------ -----------------------------------+------------------------+-------+ Clock Signal | Clock buffer(FF name) | Load | -----------------------------------+------------------------+-------+ clk | BUFGP | 4 | -----------------------------------+------------------------+-------+ Timing Summary: --------------- Speed Grade: -4 Minimum period: 1.939ns (Maximum Frequency: 515.730MHz) Minimum input arrival time before clock: 4.192ns Maximum output required time after clock: 6.060ns Maximum combinational path delay: No path found ========================================================================= Completed process "Synthesize". Started process "Translate". Command Line: ngdbuild -intstyle ise -dd z:\camurati\esercitazione_2/_ngo -i -p xc3s200-ft256-4 datapath.ngc datapath.ngd Reading NGO file "Z:/camurati/esercitazione_2/datapath.ngc" ... Reading component libraries for design expansion... Checking timing specifications ... Checking expanded design ... NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0 Total memory usage is 38140 kilobytes Writing NGD file "datapath.ngd" ... Writing NGDBUILD log file "datapath.bld"... NGDBUILD done. Completed process "Translate". Started process "Map". Using target part "3s200ft256-4". Removing unused or disabled logic... Running cover... Running directed packing... Running delay-based LUT packing... Running related packing... Design Summary: Number of errors: 0 Number of warnings: 0 Logic Utilization: Number of Slice Flip Flops: 4 out of 3,840 1% Number of 4 input LUTs: 10 out of 3,840 1% Logic Distribution: Number of occupied Slices: 6 out of 1,920 1% Number of Slices containing only related logic: 6 out of 6 100% Number of Slices containing unrelated logic: 0 out of 6 0% *See NOTES below for an explanation of the effects of unrelated logic Total Number of 4 input LUTs: 10 out of 3,840 1% Number of bonded IOBs: 11 out of 173 6% Number of GCLKs: 1 out of 8 12% Total equivalent gate count for design: 95 Additional JTAG gate count for IOBs: 528 Peak Memory Usage: 66 MB NOTES: Related logic is defined as being logic that shares connectivity - e.g. two LUTs are "related" if they share common inputs. When assembling slices, Map gives priority to combine logic that is related. Doing so results in the best timing performance. Unrelated logic shares no connectivity. Map will only begin packing unrelated logic into a slice once 99% of the slices are occupied through related logic packing. Note that once logic distribution reaches the 99% level through related logic packing, this does not mean the device is completely utilized. Unrelated logic packing will then begin, continuing until all usable LUTs and FFs are occupied. Depending on your timing budget, increased levels of unrelated logic packing may adversely affect the overall timing performance of your design. Mapping completed. See MAP report file "datapath_map.mrp" for details. Completed process "Map". Mapping Module datapath . . . MAP command line: map -intstyle ise -p xc3s200-ft256-4 -cm area -pr b -k 4 -c 100 -tx off -o datapath_map.ncd datapath.ngd datapath.pcf Mapping Module datapath: DONE Started process "Place & Route". Constraints file: datapath.pcf Loading device database for application Par from file "datapath_map.ncd". "datapath" is an NCD, version 2.38, device xc3s200, package ft256, speed -4 Loading device for application Par from file '3s200.nph' in environment C:/Program Files/Xilinx. Device speed data version: PRODUCTION 1.32 2004-06-25. Resolving physical constraints. Finished resolving physical constraints. Device utilization summary: Number of External IOBs 11 out of 173 6% Number of LOCed External IOBs 0 out of 11 0% Number of Slices 6 out of 1920 1% Number of BUFGMUXs 1 out of 8 12% Overall effort level (-ol): Standard (set by user) Placer effort level (-pl): Standard (set by user) Placer cost table entry (-t): 1 Router effort level (-rl): Standard (set by user) Phase 1.1 Phase 1.1 (Checksum:9896b5) REAL time: 0 secs . Phase 3.3 Phase 3.3 (Checksum:1c9c37d) REAL time: 0 secs Phase 4.5 Phase 4.5 (Checksum:26259fc) REAL time: 0 secs Phase 5.8 . Phase 5.8 (Checksum:98d9e1) REAL time: 0 secs Phase 6.5 Phase 6.5 (Checksum:39386fa) REAL time: 0 secs Phase 7.18 Phase 7.18 (Checksum:42c1d79) REAL time: 0 secs Writing design to file datapath.ncd. Total REAL time to Placer completion: 0 secs Total CPU time to Placer completion: 0 secs Phase 1: 53 unrouted; REAL time: 0 secs Phase 2: 48 unrouted; REAL time: 0 secs Phase 3: 20 unrouted; REAL time: 0 secs Phase 4: 0 unrouted; REAL time: 0 secs Total REAL time to Router completion: 0 secs Total CPU time to Router completion: 0 secs Generating "par" statistics. ************************** Generating Clock Report ************************** +-------------------------+----------+------+------+------------+-------------+ | Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)| +-------------------------+----------+------+------+------------+-------------+ | clk_BUFGP | BUFGMUX0| No | 4 | 0.000 | 1.010 | +-------------------------+----------+------+------+------------+-------------+ Generating Pad Report. All signals are completely routed. Total REAL time to PAR completion: 4 secs Total CPU time to PAR completion: 1 secs Peak Memory Usage: 56 MB Placement: Completed - No errors found. Routing: Completed - No errors found. Writing design to file datapath.ncd. PAR done. Completed process "Place & Route". Started process "Generate Post-Place & Route Static Timing". Analysis completed Fri Mar 16 11:13:23 2007 -------------------------------------------------------------------------------- Generating Report ... Completed process "Generate Post-Place & Route Static Timing". Place & Route Module datapath . . . PAR command line: par -w -intstyle ise -ol std -t 1 datapath_map.ncd datapath.ncd datapath.pcf PAR completed successfully Started process "Generate Post-Place & Route Simulation Model". Completed process "Generate Post-Place & Route Simulation Model". Compiling vhdl file Z:/camurati/esercitazione_2/datapath.vhd in Library work. Entity (Architecture ) compiled. Project Navigator Auto-Make Log File ------------------------------------- Compiling vhdl file Z:/camurati/esercitazione_2/datapath.vhd in Library work. Entity (Architecture ) compiled. Project Navigator Auto-Make Log File ------------------------------------- Compiling vhdl file Z:/camurati/esercitazione_2/datapath.vhd in Library work. Entity (Architecture ) compiled. Project Navigator Auto-Make Log File ------------------------------------- Compiling vhdl file Z:/camurati/esercitazione_2/datapath.vhd in Library work. Entity (Architecture ) compiled. Project Navigator Auto-Make Log File ------------------------------------- Compiling vhdl file Z:/camurati/esercitazione_2/datapath.vhd in Library work. Entity (Architecture ) compiled. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file Z:/camurati/esercitazione_2/datapath.vhd in Library work. Entity (Architecture ) compiled. ========================================================================= * HDL Analysis * ========================================================================= Analyzing Entity (Architecture ). Entity analyzed. Unit generated. ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is Z:/camurati/esercitazione_2/datapath.vhd. Found 1-bit register for signal . Found 3-bit register for signal . Summary: inferred 4 D-type flip-flop(s). Unit synthesized. ========================================================================= * Advanced HDL Synthesis * ========================================================================= Advanced RAM inference ... Advanced multiplier inference ... Advanced Registered AddSub inference ... Dynamic shift register inference ... ========================================================================= HDL Synthesis Report Macro Statistics # Registers : 2 1-bit register : 1 3-bit register : 1 ========================================================================= ========================================================================= * Low Level Synthesis * ========================================================================= Optimizing unit ... Loading device for application Xst from file '3s200.nph' in environment C:/Program Files/Xilinx. Mapping all equations... Building and optimizing final netlist ... Found area constraint ratio of 100 (+ 5) on block datapath, actual ratio is 0. ========================================================================= * Final Report * ========================================================================= Device utilization summary: --------------------------- Selected Device : 3s200ft256-4 Number of Slices: 5 out of 1920 0% Number of Slice Flip Flops: 4 out of 3840 0% Number of 4 input LUTs: 9 out of 3840 0% Number of bonded IOBs: 10 out of 173 5% Number of GCLKs: 1 out of 8 12% ========================================================================= TIMING REPORT Clock Information: ------------------ -----------------------------------+------------------------+-------+ Clock Signal | Clock buffer(FF name) | Load | -----------------------------------+------------------------+-------+ clk | BUFGP | 4 | -----------------------------------+------------------------+-------+ Timing Summary: --------------- Speed Grade: -4 Minimum period: 1.939ns (Maximum Frequency: 515.730MHz) Minimum input arrival time before clock: 4.192ns Maximum output required time after clock: 6.060ns Maximum combinational path delay: No path found ========================================================================= Completed process "Synthesize". Started process "Translate". Command Line: ngdbuild -intstyle ise -dd z:\camurati\esercitazione_2/_ngo -i -p xc3s200-ft256-4 datapath.ngc datapath.ngd Reading NGO file "Z:/camurati/esercitazione_2/datapath.ngc" ... Reading component libraries for design expansion... Checking timing specifications ... Checking expanded design ... NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0 Total memory usage is 38140 kilobytes Writing NGD file "datapath.ngd" ... Writing NGDBUILD log file "datapath.bld"... NGDBUILD done. Completed process "Translate". Started process "Map". Using target part "3s200ft256-4". Removing unused or disabled logic... Running cover... Running directed packing... Running delay-based LUT packing... Running related packing... Design Summary: Number of errors: 0 Number of warnings: 0 Logic Utilization: Number of Slice Flip Flops: 4 out of 3,840 1% Number of 4 input LUTs: 9 out of 3,840 1% Logic Distribution: Number of occupied Slices: 5 out of 1,920 1% Number of Slices containing only related logic: 5 out of 5 100% Number of Slices containing unrelated logic: 0 out of 5 0% *See NOTES below for an explanation of the effects of unrelated logic Total Number of 4 input LUTs: 9 out of 3,840 1% Number of bonded IOBs: 11 out of 173 6% Number of GCLKs: 1 out of 8 12% Total equivalent gate count for design: 89 Additional JTAG gate count for IOBs: 528 Peak Memory Usage: 66 MB NOTES: Related logic is defined as being logic that shares connectivity - e.g. two LUTs are "related" if they share common inputs. When assembling slices, Map gives priority to combine logic that is related. Doing so results in the best timing performance. Unrelated logic shares no connectivity. Map will only begin packing unrelated logic into a slice once 99% of the slices are occupied through related logic packing. Note that once logic distribution reaches the 99% level through related logic packing, this does not mean the device is completely utilized. Unrelated logic packing will then begin, continuing until all usable LUTs and FFs are occupied. Depending on your timing budget, increased levels of unrelated logic packing may adversely affect the overall timing performance of your design. Mapping completed. See MAP report file "datapath_map.mrp" for details. Completed process "Map". Mapping Module datapath . . . MAP command line: map -intstyle ise -p xc3s200-ft256-4 -cm area -pr b -k 4 -c 100 -tx off -o datapath_map.ncd datapath.ngd datapath.pcf Mapping Module datapath: DONE Started process "Place & Route". Constraints file: datapath.pcf Loading device database for application Par from file "datapath_map.ncd". "datapath" is an NCD, version 2.38, device xc3s200, package ft256, speed -4 Loading device for application Par from file '3s200.nph' in environment C:/Program Files/Xilinx. Device speed data version: PRODUCTION 1.32 2004-06-25. Resolving physical constraints. Finished resolving physical constraints. Device utilization summary: Number of External IOBs 11 out of 173 6% Number of LOCed External IOBs 0 out of 11 0% Number of Slices 5 out of 1920 1% Number of BUFGMUXs 1 out of 8 12% Overall effort level (-ol): Standard (set by user) Placer effort level (-pl): Standard (set by user) Placer cost table entry (-t): 1 Router effort level (-rl): Standard (set by user) Phase 1.1 Phase 1.1 (Checksum:9896b2) REAL time: 0 secs Phase 3.3 Phase 3.3 (Checksum:1c9c37d) REAL time: 0 secs Phase 4.5 Phase 4.5 (Checksum:26259fc) REAL time: 0 secs Phase 5.8 . Phase 5.8 (Checksum:98ac2d) REAL time: 0 secs Phase 6.5 Phase 6.5 (Checksum:39386fa) REAL time: 0 secs Phase 7.18 Phase 7.18 (Checksum:42c1d79) REAL time: 0 secs Writing design to file datapath.ncd. Total REAL time to Placer completion: 0 secs Total CPU time to Placer completion: 0 secs Phase 1: 52 unrouted; REAL time: 0 secs Phase 2: 47 unrouted; REAL time: 0 secs Phase 3: 14 unrouted; REAL time: 0 secs Phase 4: 0 unrouted; REAL time: 0 secs Total REAL time to Router completion: 0 secs Total CPU time to Router completion: 0 secs Generating "par" statistics. ************************** Generating Clock Report ************************** +-------------------------+----------+------+------+------------+-------------+ | Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)| +-------------------------+----------+------+------+------------+-------------+ | clk_BUFGP | BUFGMUX7| No | 4 | 0.000 | 1.011 | +-------------------------+----------+------+------+------------+-------------+ Generating Pad Report. All signals are completely routed. Total REAL time to PAR completion: 4 secs Total CPU time to PAR completion: 1 secs Peak Memory Usage: 56 MB Placement: Completed - No errors found. Routing: Completed - No errors found. Writing design to file datapath.ncd. PAR done. Completed process "Place & Route". Started process "Generate Post-Place & Route Static Timing". Analysis completed Fri Mar 16 11:31:09 2007 -------------------------------------------------------------------------------- Generating Report ... Completed process "Generate Post-Place & Route Static Timing". Place & Route Module datapath . . . PAR command line: par -w -intstyle ise -ol std -t 1 datapath_map.ncd datapath.ncd datapath.pcf PAR completed successfully Started process "Generate Post-Place & Route Simulation Model". Completed process "Generate Post-Place & Route Simulation Model". Compiling vhdl file Z:/camurati/esercitazione_2/datapath.vhd in Library work. Entity (Architecture ) compiled. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file Z:/camurati/esercitazione_2/datapath.vhd in Library work. Entity (Architecture ) compiled. ========================================================================= * HDL Analysis * ========================================================================= Analyzing Entity (Architecture ). INFO:Xst:1304 - Contents of register in unit never changes during circuit operation. The register is replaced by logic. Entity analyzed. Unit generated. ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is Z:/camurati/esercitazione_2/datapath.vhd. Found 3-bit register for signal . Summary: inferred 3 D-type flip-flop(s). Unit synthesized. ========================================================================= * Advanced HDL Synthesis * ========================================================================= Advanced RAM inference ... Advanced multiplier inference ... Advanced Registered AddSub inference ... Dynamic shift register inference ... ========================================================================= HDL Synthesis Report Macro Statistics # Registers : 1 3-bit register : 1 ========================================================================= ========================================================================= * Low Level Synthesis * ========================================================================= Optimizing unit ... Loading device for application Xst from file '3s200.nph' in environment C:/Program Files/Xilinx. Mapping all equations... Building and optimizing final netlist ... Found area constraint ratio of 100 (+ 5) on block datapath, actual ratio is 0. ========================================================================= * Final Report * ========================================================================= Device utilization summary: --------------------------- Selected Device : 3s200ft256-4 Number of Slices: 4 out of 1920 0% Number of Slice Flip Flops: 3 out of 3840 0% Number of 4 input LUTs: 8 out of 3840 0% Number of bonded IOBs: 10 out of 173 5% Number of GCLKs: 1 out of 8 12% ========================================================================= TIMING REPORT Clock Information: ------------------ -----------------------------------+------------------------+-------+ Clock Signal | Clock buffer(FF name) | Load | -----------------------------------+------------------------+-------+ clk | BUFGP | 3 | -----------------------------------+------------------------+-------+ Timing Summary: --------------- Speed Grade: -4 Minimum period: 1.939ns (Maximum Frequency: 515.730MHz) Minimum input arrival time before clock: 4.163ns Maximum output required time after clock: 6.060ns Maximum combinational path delay: No path found ========================================================================= Completed process "Synthesize". Started process "Translate". Command Line: ngdbuild -intstyle ise -dd z:\camurati\esercitazione_2/_ngo -i -p xc3s200-ft256-4 datapath.ngc datapath.ngd Reading NGO file "Z:/camurati/esercitazione_2/datapath.ngc" ... Reading component libraries for design expansion... Checking timing specifications ... Checking expanded design ... NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0 Total memory usage is 38140 kilobytes Writing NGD file "datapath.ngd" ... Writing NGDBUILD log file "datapath.bld"... NGDBUILD done. Completed process "Translate". Started process "Map". Using target part "3s200ft256-4". Removing unused or disabled logic... Running cover... Running directed packing... Running delay-based LUT packing... Running related packing... Design Summary: Number of errors: 0 Number of warnings: 0 Logic Utilization: Number of Slice Flip Flops: 3 out of 3,840 1% Number of 4 input LUTs: 8 out of 3,840 1% Logic Distribution: Number of occupied Slices: 4 out of 1,920 1% Number of Slices containing only related logic: 4 out of 4 100% Number of Slices containing unrelated logic: 0 out of 4 0% *See NOTES below for an explanation of the effects of unrelated logic Total Number of 4 input LUTs: 8 out of 3,840 1% Number of bonded IOBs: 11 out of 173 6% Number of GCLKs: 1 out of 8 12% Total equivalent gate count for design: 75 Additional JTAG gate count for IOBs: 528 Peak Memory Usage: 66 MB NOTES: Related logic is defined as being logic that shares connectivity - e.g. two LUTs are "related" if they share common inputs. When assembling slices, Map gives priority to combine logic that is related. Doing so results in the best timing performance. Unrelated logic shares no connectivity. Map will only begin packing unrelated logic into a slice once 99% of the slices are occupied through related logic packing. Note that once logic distribution reaches the 99% level through related logic packing, this does not mean the device is completely utilized. Unrelated logic packing will then begin, continuing until all usable LUTs and FFs are occupied. Depending on your timing budget, increased levels of unrelated logic packing may adversely affect the overall timing performance of your design. Mapping completed. See MAP report file "datapath_map.mrp" for details. Completed process "Map". Mapping Module datapath . . . MAP command line: map -intstyle ise -p xc3s200-ft256-4 -cm area -pr b -k 4 -c 100 -tx off -o datapath_map.ncd datapath.ngd datapath.pcf Mapping Module datapath: DONE Started process "Place & Route". Constraints file: datapath.pcf Loading device database for application Par from file "datapath_map.ncd". "datapath" is an NCD, version 2.38, device xc3s200, package ft256, speed -4 Loading device for application Par from file '3s200.nph' in environment C:/Program Files/Xilinx. Device speed data version: PRODUCTION 1.32 2004-06-25. Resolving physical constraints. Finished resolving physical constraints. Device utilization summary: Number of External IOBs 11 out of 173 6% Number of LOCed External IOBs 0 out of 11 0% Number of Slices 4 out of 1920 1% Number of BUFGMUXs 1 out of 8 12% Overall effort level (-ol): Standard (set by user) Placer effort level (-pl): Standard (set by user) Placer cost table entry (-t): 1 Router effort level (-rl): Standard (set by user) Phase 1.1 Phase 1.1 (Checksum:9896af) REAL time: 0 secs Phase 3.3 Phase 3.3 (Checksum:1c9c37d) REAL time: 0 secs Phase 4.5 Phase 4.5 (Checksum:26259fc) REAL time: 0 secs Phase 5.8 . Phase 5.8 (Checksum:98b9a7) REAL time: 0 secs Phase 6.5 Phase 6.5 (Checksum:39386fa) REAL time: 0 secs Phase 7.18 Phase 7.18 (Checksum:42c1d79) REAL time: 0 secs Writing design to file datapath.ncd. Total REAL time to Placer completion: 0 secs Total CPU time to Placer completion: 0 secs Phase 1: 45 unrouted; REAL time: 0 secs Phase 2: 41 unrouted; REAL time: 0 secs Phase 3: 10 unrouted; REAL time: 0 secs Phase 4: 0 unrouted; REAL time: 0 secs Total REAL time to Router completion: 0 secs Total CPU time to Router completion: 0 secs Generating "par" statistics. ************************** Generating Clock Report ************************** +-------------------------+----------+------+------+------------+-------------+ | Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)| +-------------------------+----------+------+------+------------+-------------+ | clk_BUFGP | BUFGMUX7| No | 3 | 0.000 | 1.011 | +-------------------------+----------+------+------+------------+-------------+ Generating Pad Report. All signals are completely routed. Total REAL time to PAR completion: 4 secs Total CPU time to PAR completion: 1 secs Peak Memory Usage: 56 MB Placement: Completed - No errors found. Routing: Completed - No errors found. Writing design to file datapath.ncd. PAR done. Completed process "Place & Route". Started process "Generate Post-Place & Route Static Timing". Analysis completed Fri Mar 16 11:35:18 2007 -------------------------------------------------------------------------------- Generating Report ... Completed process "Generate Post-Place & Route Static Timing". Place & Route Module datapath . . . PAR command line: par -w -intstyle ise -ol std -t 1 datapath_map.ncd datapath.ncd datapath.pcf PAR completed successfully Started process "Generate Post-Place & Route Simulation Model". Completed process "Generate Post-Place & Route Simulation Model". Compiling vhdl file Z:/camurati/esercitazione_2/datapath.vhd in Library work. Entity (Architecture ) compiled. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file Z:/camurati/esercitazione_2/datapath.vhd in Library work. Entity (Architecture ) compiled. ========================================================================= * HDL Analysis * ========================================================================= Analyzing Entity (Architecture ). Entity analyzed. Unit generated. ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is Z:/camurati/esercitazione_2/datapath.vhd. Found 1-bit register for signal . Found 3-bit register for signal . Summary: inferred 4 D-type flip-flop(s). Unit synthesized. ========================================================================= * Advanced HDL Synthesis * ========================================================================= Advanced RAM inference ... Advanced multiplier inference ... Advanced Registered AddSub inference ... Dynamic shift register inference ... ========================================================================= HDL Synthesis Report Macro Statistics # Registers : 2 1-bit register : 1 3-bit register : 1 ========================================================================= ========================================================================= * Low Level Synthesis * ========================================================================= Optimizing unit ... Loading device for application Xst from file '3s200.nph' in environment C:/Program Files/Xilinx. Mapping all equations... Building and optimizing final netlist ... Found area constraint ratio of 100 (+ 5) on block datapath, actual ratio is 0. ========================================================================= * Final Report * ========================================================================= Device utilization summary: --------------------------- Selected Device : 3s200ft256-4 Number of Slices: 5 out of 1920 0% Number of Slice Flip Flops: 4 out of 3840 0% Number of 4 input LUTs: 9 out of 3840 0% Number of bonded IOBs: 10 out of 173 5% Number of GCLKs: 1 out of 8 12% ========================================================================= TIMING REPORT Clock Information: ------------------ -----------------------------------+------------------------+-------+ Clock Signal | Clock buffer(FF name) | Load | -----------------------------------+------------------------+-------+ clk | BUFGP | 4 | -----------------------------------+------------------------+-------+ Timing Summary: --------------- Speed Grade: -4 Minimum period: 1.939ns (Maximum Frequency: 515.730MHz) Minimum input arrival time before clock: 4.192ns Maximum output required time after clock: 6.060ns Maximum combinational path delay: No path found ========================================================================= Completed process "Synthesize". Started process "Translate". Command Line: ngdbuild -intstyle ise -dd z:\camurati\esercitazione_2/_ngo -i -p xc3s200-ft256-4 datapath.ngc datapath.ngd Reading NGO file "Z:/camurati/esercitazione_2/datapath.ngc" ... Reading component libraries for design expansion... Checking timing specifications ... Checking expanded design ... NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0 Total memory usage is 38140 kilobytes Writing NGD file "datapath.ngd" ... Writing NGDBUILD log file "datapath.bld"... NGDBUILD done. Completed process "Translate". Started process "Map". Using target part "3s200ft256-4". Removing unused or disabled logic... Running cover... Running directed packing... Running delay-based LUT packing... Running related packing... Design Summary: Number of errors: 0 Number of warnings: 0 Logic Utilization: Number of Slice Flip Flops: 4 out of 3,840 1% Number of 4 input LUTs: 9 out of 3,840 1% Logic Distribution: Number of occupied Slices: 5 out of 1,920 1% Number of Slices containing only related logic: 5 out of 5 100% Number of Slices containing unrelated logic: 0 out of 5 0% *See NOTES below for an explanation of the effects of unrelated logic Total Number of 4 input LUTs: 9 out of 3,840 1% Number of bonded IOBs: 11 out of 173 6% Number of GCLKs: 1 out of 8 12% Total equivalent gate count for design: 89 Additional JTAG gate count for IOBs: 528 Peak Memory Usage: 66 MB NOTES: Related logic is defined as being logic that shares connectivity - e.g. two LUTs are "related" if they share common inputs. When assembling slices, Map gives priority to combine logic that is related. Doing so results in the best timing performance. Unrelated logic shares no connectivity. Map will only begin packing unrelated logic into a slice once 99% of the slices are occupied through related logic packing. Note that once logic distribution reaches the 99% level through related logic packing, this does not mean the device is completely utilized. Unrelated logic packing will then begin, continuing until all usable LUTs and FFs are occupied. Depending on your timing budget, increased levels of unrelated logic packing may adversely affect the overall timing performance of your design. Mapping completed. See MAP report file "datapath_map.mrp" for details. Completed process "Map". Mapping Module datapath . . . MAP command line: map -intstyle ise -p xc3s200-ft256-4 -cm area -pr b -k 4 -c 100 -tx off -o datapath_map.ncd datapath.ngd datapath.pcf Mapping Module datapath: DONE Started process "Place & Route". Constraints file: datapath.pcf Loading device database for application Par from file "datapath_map.ncd". "datapath" is an NCD, version 2.38, device xc3s200, package ft256, speed -4 Loading device for application Par from file '3s200.nph' in environment C:/Program Files/Xilinx. Device speed data version: PRODUCTION 1.32 2004-06-25. Resolving physical constraints. Finished resolving physical constraints. Device utilization summary: Number of External IOBs 11 out of 173 6% Number of LOCed External IOBs 0 out of 11 0% Number of Slices 5 out of 1920 1% Number of BUFGMUXs 1 out of 8 12% Overall effort level (-ol): Standard (set by user) Placer effort level (-pl): Standard (set by user) Placer cost table entry (-t): 1 Router effort level (-rl): Standard (set by user) Phase 1.1 Phase 1.1 (Checksum:9896b2) REAL time: 0 secs Phase 3.3 Phase 3.3 (Checksum:1c9c37d) REAL time: 0 secs Phase 4.5 Phase 4.5 (Checksum:26259fc) REAL time: 0 secs Phase 5.8 . Phase 5.8 (Checksum:98ac2d) REAL time: 0 secs Phase 6.5 Phase 6.5 (Checksum:39386fa) REAL time: 0 secs Phase 7.18 Phase 7.18 (Checksum:42c1d79) REAL time: 0 secs Writing design to file datapath.ncd. Total REAL time to Placer completion: 0 secs Total CPU time to Placer completion: 0 secs Phase 1: 52 unrouted; REAL time: 0 secs Phase 2: 47 unrouted; REAL time: 0 secs Phase 3: 8 unrouted; REAL time: 0 secs Phase 4: 0 unrouted; REAL time: 0 secs Total REAL time to Router completion: 0 secs Total CPU time to Router completion: 0 secs Generating "par" statistics. ************************** Generating Clock Report ************************** +-------------------------+----------+------+------+------------+-------------+ | Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)| +-------------------------+----------+------+------+------------+-------------+ | clk_BUFGP | BUFGMUX7| No | 4 | 0.000 | 1.011 | +-------------------------+----------+------+------+------------+-------------+ Generating Pad Report. All signals are completely routed. Total REAL time to PAR completion: 4 secs Total CPU time to PAR completion: 1 secs Peak Memory Usage: 56 MB Placement: Completed - No errors found. Routing: Completed - No errors found. Writing design to file datapath.ncd. PAR done. Completed process "Place & Route". Started process "Generate Post-Place & Route Static Timing". Analysis completed Fri Mar 16 11:36:24 2007 -------------------------------------------------------------------------------- Generating Report ... Completed process "Generate Post-Place & Route Static Timing". Place & Route Module datapath . . . PAR command line: par -w -intstyle ise -ol std -t 1 datapath_map.ncd datapath.ncd datapath.pcf PAR completed successfully Started process "Generate Post-Place & Route Simulation Model". Completed process "Generate Post-Place & Route Simulation Model". Compiling vhdl file Z:/camurati/esercitazione_2/datapath.vhd in Library work. Entity (Architecture ) compiled. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file Z:/camurati/esercitazione_2/datapath.vhd in Library work. Entity (Architecture ) compiled. ========================================================================= * HDL Analysis * ========================================================================= Analyzing Entity (Architecture ). Entity analyzed. Unit generated. ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is Z:/camurati/esercitazione_2/datapath.vhd. Found 1-bit register for signal . Found 3-bit register for signal . Summary: inferred 4 D-type flip-flop(s). Unit synthesized. ========================================================================= * Advanced HDL Synthesis * ========================================================================= Advanced RAM inference ... Advanced multiplier inference ... Advanced Registered AddSub inference ... Dynamic shift register inference ... ========================================================================= HDL Synthesis Report Macro Statistics # Registers : 2 1-bit register : 1 3-bit register : 1 ========================================================================= ========================================================================= * Low Level Synthesis * ========================================================================= Optimizing unit ... Loading device for application Xst from file '3s200.nph' in environment C:/Program Files/Xilinx. Mapping all equations... Building and optimizing final netlist ... Found area constraint ratio of 100 (+ 5) on block datapath, actual ratio is 0. ========================================================================= * Final Report * ========================================================================= Device utilization summary: --------------------------- Selected Device : 3s200ft256-4 Number of Slices: 5 out of 1920 0% Number of Slice Flip Flops: 4 out of 3840 0% Number of 4 input LUTs: 9 out of 3840 0% Number of bonded IOBs: 10 out of 173 5% Number of GCLKs: 1 out of 8 12% ========================================================================= TIMING REPORT Clock Information: ------------------ -----------------------------------+------------------------+-------+ Clock Signal | Clock buffer(FF name) | Load | -----------------------------------+------------------------+-------+ clk | BUFGP | 4 | -----------------------------------+------------------------+-------+ Timing Summary: --------------- Speed Grade: -4 Minimum period: 1.939ns (Maximum Frequency: 515.730MHz) Minimum input arrival time before clock: 4.192ns Maximum output required time after clock: 6.060ns Maximum combinational path delay: No path found ========================================================================= Completed process "Synthesize". Started process "Translate". Command Line: ngdbuild -intstyle ise -dd z:\camurati\esercitazione_2/_ngo -i -p xc3s200-ft256-4 datapath.ngc datapath.ngd Reading NGO file "Z:/camurati/esercitazione_2/datapath.ngc" ... Reading component libraries for design expansion... Checking timing specifications ... Checking expanded design ... NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0 Total memory usage is 38140 kilobytes Writing NGD file "datapath.ngd" ... Writing NGDBUILD log file "datapath.bld"... NGDBUILD done. Completed process "Translate". Started process "Map". Using target part "3s200ft256-4". Removing unused or disabled logic... Running cover... Running directed packing... Running delay-based LUT packing... Running related packing... Design Summary: Number of errors: 0 Number of warnings: 0 Logic Utilization: Number of Slice Flip Flops: 4 out of 3,840 1% Number of 4 input LUTs: 9 out of 3,840 1% Logic Distribution: Number of occupied Slices: 5 out of 1,920 1% Number of Slices containing only related logic: 5 out of 5 100% Number of Slices containing unrelated logic: 0 out of 5 0% *See NOTES below for an explanation of the effects of unrelated logic Total Number of 4 input LUTs: 9 out of 3,840 1% Number of bonded IOBs: 11 out of 173 6% Number of GCLKs: 1 out of 8 12% Total equivalent gate count for design: 89 Additional JTAG gate count for IOBs: 528 Peak Memory Usage: 66 MB NOTES: Related logic is defined as being logic that shares connectivity - e.g. two LUTs are "related" if they share common inputs. When assembling slices, Map gives priority to combine logic that is related. Doing so results in the best timing performance. Unrelated logic shares no connectivity. Map will only begin packing unrelated logic into a slice once 99% of the slices are occupied through related logic packing. Note that once logic distribution reaches the 99% level through related logic packing, this does not mean the device is completely utilized. Unrelated logic packing will then begin, continuing until all usable LUTs and FFs are occupied. Depending on your timing budget, increased levels of unrelated logic packing may adversely affect the overall timing performance of your design. Mapping completed. See MAP report file "datapath_map.mrp" for details. Completed process "Map". Mapping Module datapath . . . MAP command line: map -intstyle ise -p xc3s200-ft256-4 -cm area -pr b -k 4 -c 100 -tx off -o datapath_map.ncd datapath.ngd datapath.pcf Mapping Module datapath: DONE Started process "Place & Route". Constraints file: datapath.pcf Loading device database for application Par from file "datapath_map.ncd". "datapath" is an NCD, version 2.38, device xc3s200, package ft256, speed -4 Loading device for application Par from file '3s200.nph' in environment C:/Program Files/Xilinx. Device speed data version: PRODUCTION 1.32 2004-06-25. Resolving physical constraints. Finished resolving physical constraints. Device utilization summary: Number of External IOBs 11 out of 173 6% Number of LOCed External IOBs 0 out of 11 0% Number of Slices 5 out of 1920 1% Number of BUFGMUXs 1 out of 8 12% Overall effort level (-ol): Standard (set by user) Placer effort level (-pl): Standard (set by user) Placer cost table entry (-t): 1 Router effort level (-rl): Standard (set by user) Phase 1.1 Phase 1.1 (Checksum:9896b2) REAL time: 0 secs Phase 3.3 Phase 3.3 (Checksum:1c9c37d) REAL time: 0 secs Phase 4.5 Phase 4.5 (Checksum:26259fc) REAL time: 0 secs Phase 5.8 . Phase 5.8 (Checksum:98ac2d) REAL time: 0 secs Phase 6.5 Phase 6.5 (Checksum:39386fa) REAL time: 0 secs Phase 7.18 Phase 7.18 (Checksum:42c1d79) REAL time: 0 secs Writing design to file datapath.ncd. Total REAL time to Placer completion: 0 secs Total CPU time to Placer completion: 0 secs Phase 1: 52 unrouted; REAL time: 0 secs Phase 2: 47 unrouted; REAL time: 0 secs Phase 3: 8 unrouted; REAL time: 0 secs Phase 4: 0 unrouted; REAL time: 0 secs Total REAL time to Router completion: 0 secs Total CPU time to Router completion: 0 secs Generating "par" statistics. ************************** Generating Clock Report ************************** +-------------------------+----------+------+------+------------+-------------+ | Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)| +-------------------------+----------+------+------+------------+-------------+ | clk_BUFGP | BUFGMUX7| No | 4 | 0.000 | 1.011 | +-------------------------+----------+------+------+------------+-------------+ Generating Pad Report. All signals are completely routed. Total REAL time to PAR completion: 4 secs Total CPU time to PAR completion: 1 secs Peak Memory Usage: 56 MB Placement: Completed - No errors found. Routing: Completed - No errors found. Writing design to file datapath.ncd. PAR done. Completed process "Place & Route". Started process "Generate Post-Place & Route Static Timing". Analysis completed Fri Mar 16 11:37:29 2007 -------------------------------------------------------------------------------- Generating Report ... Completed process "Generate Post-Place & Route Static Timing". Place & Route Module datapath . . . PAR command line: par -w -intstyle ise -ol std -t 1 datapath_map.ncd datapath.ncd datapath.pcf PAR completed successfully Started process "Generate Post-Place & Route Simulation Model". Completed process "Generate Post-Place & Route Simulation Model". Compiling vhdl file Z:/camurati/esercitazione_2/datapath.vhd in Library work. Entity (Architecture ) compiled. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file Z:/camurati/esercitazione_2/datapath.vhd in Library work. Entity (Architecture ) compiled. ========================================================================= * HDL Analysis * ========================================================================= Analyzing Entity (Architecture ). Entity analyzed. Unit generated. ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is Z:/camurati/esercitazione_2/datapath.vhd. Found 1-bit register for signal . Found 3-bit register for signal . Summary: inferred 4 D-type flip-flop(s). Unit synthesized. ========================================================================= * Advanced HDL Synthesis * ========================================================================= Advanced RAM inference ... Advanced multiplier inference ... Advanced Registered AddSub inference ... Dynamic shift register inference ... ========================================================================= HDL Synthesis Report Macro Statistics # Registers : 2 1-bit register : 1 3-bit register : 1 ========================================================================= ========================================================================= * Low Level Synthesis * ========================================================================= Optimizing unit ... Loading device for application Xst from file '3s200.nph' in environment C:/Program Files/Xilinx. Mapping all equations... Building and optimizing final netlist ... Found area constraint ratio of 100 (+ 5) on block datapath, actual ratio is 0. ========================================================================= * Final Report * ========================================================================= Device utilization summary: --------------------------- Selected Device : 3s200ft256-4 Number of Slices: 5 out of 1920 0% Number of Slice Flip Flops: 4 out of 3840 0% Number of 4 input LUTs: 9 out of 3840 0% Number of bonded IOBs: 10 out of 173 5% Number of GCLKs: 1 out of 8 12% ========================================================================= TIMING REPORT Clock Information: ------------------ -----------------------------------+------------------------+-------+ Clock Signal | Clock buffer(FF name) | Load | -----------------------------------+------------------------+-------+ clk | BUFGP | 4 | -----------------------------------+------------------------+-------+ Timing Summary: --------------- Speed Grade: -4 Minimum period: 1.939ns (Maximum Frequency: 515.730MHz) Minimum input arrival time before clock: 4.192ns Maximum output required time after clock: 6.060ns Maximum combinational path delay: No path found ========================================================================= Completed process "Synthesize". Started process "Translate". Command Line: ngdbuild -intstyle ise -dd z:\camurati\esercitazione_2/_ngo -i -p xc3s200-ft256-4 datapath.ngc datapath.ngd Reading NGO file "Z:/camurati/esercitazione_2/datapath.ngc" ... Reading component libraries for design expansion... Checking timing specifications ... Checking expanded design ... NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0 Total memory usage is 38140 kilobytes Writing NGD file "datapath.ngd" ... Writing NGDBUILD log file "datapath.bld"... NGDBUILD done. Completed process "Translate". Started process "Map". Using target part "3s200ft256-4". Removing unused or disabled logic... Running cover... Running directed packing... Running delay-based LUT packing... Running related packing... Design Summary: Number of errors: 0 Number of warnings: 0 Logic Utilization: Number of Slice Flip Flops: 4 out of 3,840 1% Number of 4 input LUTs: 9 out of 3,840 1% Logic Distribution: Number of occupied Slices: 5 out of 1,920 1% Number of Slices containing only related logic: 5 out of 5 100% Number of Slices containing unrelated logic: 0 out of 5 0% *See NOTES below for an explanation of the effects of unrelated logic Total Number of 4 input LUTs: 9 out of 3,840 1% Number of bonded IOBs: 11 out of 173 6% Number of GCLKs: 1 out of 8 12% Total equivalent gate count for design: 89 Additional JTAG gate count for IOBs: 528 Peak Memory Usage: 66 MB NOTES: Related logic is defined as being logic that shares connectivity - e.g. two LUTs are "related" if they share common inputs. When assembling slices, Map gives priority to combine logic that is related. Doing so results in the best timing performance. Unrelated logic shares no connectivity. Map will only begin packing unrelated logic into a slice once 99% of the slices are occupied through related logic packing. Note that once logic distribution reaches the 99% level through related logic packing, this does not mean the device is completely utilized. Unrelated logic packing will then begin, continuing until all usable LUTs and FFs are occupied. Depending on your timing budget, increased levels of unrelated logic packing may adversely affect the overall timing performance of your design. Mapping completed. See MAP report file "datapath_map.mrp" for details. Completed process "Map". Mapping Module datapath . . . MAP command line: map -intstyle ise -p xc3s200-ft256-4 -cm area -pr b -k 4 -c 100 -tx off -o datapath_map.ncd datapath.ngd datapath.pcf Mapping Module datapath: DONE Started process "Place & Route". Constraints file: datapath.pcf Loading device database for application Par from file "datapath_map.ncd". "datapath" is an NCD, version 2.38, device xc3s200, package ft256, speed -4 Loading device for application Par from file '3s200.nph' in environment C:/Program Files/Xilinx. Device speed data version: PRODUCTION 1.32 2004-06-25. Resolving physical constraints. Finished resolving physical constraints. Device utilization summary: Number of External IOBs 11 out of 173 6% Number of LOCed External IOBs 0 out of 11 0% Number of Slices 5 out of 1920 1% Number of BUFGMUXs 1 out of 8 12% Overall effort level (-ol): Standard (set by user) Placer effort level (-pl): Standard (set by user) Placer cost table entry (-t): 1 Router effort level (-rl): Standard (set by user) Phase 1.1 Phase 1.1 (Checksum:9896b2) REAL time: 0 secs Phase 3.3 Phase 3.3 (Checksum:1c9c37d) REAL time: 0 secs Phase 4.5 Phase 4.5 (Checksum:26259fc) REAL time: 0 secs Phase 5.8 . Phase 5.8 (Checksum:98ac2d) REAL time: 0 secs Phase 6.5 Phase 6.5 (Checksum:39386fa) REAL time: 0 secs Phase 7.18 Phase 7.18 (Checksum:42c1d79) REAL time: 0 secs Writing design to file datapath.ncd. Total REAL time to Placer completion: 0 secs Total CPU time to Placer completion: 0 secs Phase 1: 52 unrouted; REAL time: 0 secs Phase 2: 47 unrouted; REAL time: 0 secs Phase 3: 14 unrouted; REAL time: 0 secs Phase 4: 0 unrouted; REAL time: 0 secs Total REAL time to Router completion: 0 secs Total CPU time to Router completion: 0 secs Generating "par" statistics. ************************** Generating Clock Report ************************** +-------------------------+----------+------+------+------------+-------------+ | Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)| +-------------------------+----------+------+------+------------+-------------+ | clk_BUFGP | BUFGMUX7| No | 4 | 0.000 | 1.011 | +-------------------------+----------+------+------+------------+-------------+ Generating Pad Report. All signals are completely routed. Total REAL time to PAR completion: 4 secs Total CPU time to PAR completion: 1 secs Peak Memory Usage: 56 MB Placement: Completed - No errors found. Routing: Completed - No errors found. Writing design to file datapath.ncd. PAR done. Completed process "Place & Route". Started process "Generate Post-Place & Route Static Timing". Analysis completed Fri Mar 16 11:38:35 2007 -------------------------------------------------------------------------------- Generating Report ... Completed process "Generate Post-Place & Route Static Timing". Place & Route Module datapath . . . PAR command line: par -w -intstyle ise -ol std -t 1 datapath_map.ncd datapath.ncd datapath.pcf PAR completed successfully Started process "Generate Post-Place & Route Simulation Model". Completed process "Generate Post-Place & Route Simulation Model". Compiling vhdl file Z:/camurati/esercitazione_2/datapath.vhd in Library work. Entity (Architecture ) compiled. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file Z:/camurati/esercitazione_2/datapath.vhd in Library work. Entity (Architecture ) compiled. ========================================================================= * HDL Analysis * ========================================================================= Analyzing Entity (Architecture ). Entity analyzed. Unit generated. ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is Z:/camurati/esercitazione_2/datapath.vhd. Found 1-bit register for signal . Found 3-bit register for signal . Summary: inferred 4 D-type flip-flop(s). Unit synthesized. ========================================================================= * Advanced HDL Synthesis * ========================================================================= Advanced RAM inference ... Advanced multiplier inference ... Advanced Registered AddSub inference ... Dynamic shift register inference ... ========================================================================= HDL Synthesis Report Macro Statistics # Registers : 2 1-bit register : 1 3-bit register : 1 ========================================================================= ========================================================================= * Low Level Synthesis * ========================================================================= Optimizing unit ... Loading device for application Xst from file '3s200.nph' in environment C:/Program Files/Xilinx. Mapping all equations... Building and optimizing final netlist ... Found area constraint ratio of 100 (+ 5) on block datapath, actual ratio is 0. ========================================================================= * Final Report * ========================================================================= Device utilization summary: --------------------------- Selected Device : 3s200ft256-4 Number of Slices: 5 out of 1920 0% Number of Slice Flip Flops: 4 out of 3840 0% Number of 4 input LUTs: 9 out of 3840 0% Number of bonded IOBs: 10 out of 173 5% Number of GCLKs: 1 out of 8 12% ========================================================================= TIMING REPORT Clock Information: ------------------ -----------------------------------+------------------------+-------+ Clock Signal | Clock buffer(FF name) | Load | -----------------------------------+------------------------+-------+ clk | BUFGP | 4 | -----------------------------------+------------------------+-------+ Timing Summary: --------------- Speed Grade: -4 Minimum period: 1.939ns (Maximum Frequency: 515.730MHz) Minimum input arrival time before clock: 4.192ns Maximum output required time after clock: 6.060ns Maximum combinational path delay: No path found ========================================================================= Completed process "Synthesize". Started process "Translate". Command Line: ngdbuild -intstyle ise -dd z:\camurati\esercitazione_2/_ngo -i -p xc3s200-ft256-4 datapath.ngc datapath.ngd Reading NGO file "Z:/camurati/esercitazione_2/datapath.ngc" ... Reading component libraries for design expansion... Checking timing specifications ... Checking expanded design ... NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0 Total memory usage is 38140 kilobytes Writing NGD file "datapath.ngd" ... Writing NGDBUILD log file "datapath.bld"... NGDBUILD done. Completed process "Translate". Started process "Map". Using target part "3s200ft256-4". Removing unused or disabled logic... Running cover... Running directed packing... Running delay-based LUT packing... Running related packing... Design Summary: Number of errors: 0 Number of warnings: 0 Logic Utilization: Number of Slice Flip Flops: 4 out of 3,840 1% Number of 4 input LUTs: 9 out of 3,840 1% Logic Distribution: Number of occupied Slices: 5 out of 1,920 1% Number of Slices containing only related logic: 5 out of 5 100% Number of Slices containing unrelated logic: 0 out of 5 0% *See NOTES below for an explanation of the effects of unrelated logic Total Number of 4 input LUTs: 9 out of 3,840 1% Number of bonded IOBs: 11 out of 173 6% Number of GCLKs: 1 out of 8 12% Total equivalent gate count for design: 89 Additional JTAG gate count for IOBs: 528 Peak Memory Usage: 66 MB NOTES: Related logic is defined as being logic that shares connectivity - e.g. two LUTs are "related" if they share common inputs. When assembling slices, Map gives priority to combine logic that is related. Doing so results in the best timing performance. Unrelated logic shares no connectivity. Map will only begin packing unrelated logic into a slice once 99% of the slices are occupied through related logic packing. Note that once logic distribution reaches the 99% level through related logic packing, this does not mean the device is completely utilized. Unrelated logic packing will then begin, continuing until all usable LUTs and FFs are occupied. Depending on your timing budget, increased levels of unrelated logic packing may adversely affect the overall timing performance of your design. Mapping completed. See MAP report file "datapath_map.mrp" for details. Completed process "Map". Mapping Module datapath . . . MAP command line: map -intstyle ise -p xc3s200-ft256-4 -cm area -pr b -k 4 -c 100 -tx off -o datapath_map.ncd datapath.ngd datapath.pcf Mapping Module datapath: DONE Started process "Place & Route". Constraints file: datapath.pcf Loading device database for application Par from file "datapath_map.ncd". "datapath" is an NCD, version 2.38, device xc3s200, package ft256, speed -4 Loading device for application Par from file '3s200.nph' in environment C:/Program Files/Xilinx. Device speed data version: PRODUCTION 1.32 2004-06-25. Resolving physical constraints. Finished resolving physical constraints. Device utilization summary: Number of External IOBs 11 out of 173 6% Number of LOCed External IOBs 0 out of 11 0% Number of Slices 5 out of 1920 1% Number of BUFGMUXs 1 out of 8 12% Overall effort level (-ol): Standard (set by user) Placer effort level (-pl): Standard (set by user) Placer cost table entry (-t): 1 Router effort level (-rl): Standard (set by user) Phase 1.1 Phase 1.1 (Checksum:9896b2) REAL time: 0 secs Phase 3.3 Phase 3.3 (Checksum:1c9c37d) REAL time: 0 secs Phase 4.5 Phase 4.5 (Checksum:26259fc) REAL time: 0 secs Phase 5.8 . Phase 5.8 (Checksum:98ac2d) REAL time: 0 secs Phase 6.5 Phase 6.5 (Checksum:39386fa) REAL time: 0 secs Phase 7.18 Phase 7.18 (Checksum:42c1d79) REAL time: 0 secs Writing design to file datapath.ncd. Total REAL time to Placer completion: 0 secs Total CPU time to Placer completion: 0 secs Phase 1: 52 unrouted; REAL time: 0 secs Phase 2: 47 unrouted; REAL time: 0 secs Phase 3: 14 unrouted; REAL time: 0 secs Phase 4: 0 unrouted; REAL time: 0 secs Total REAL time to Router completion: 0 secs Total CPU time to Router completion: 0 secs Generating "par" statistics. ************************** Generating Clock Report ************************** +-------------------------+----------+------+------+------------+-------------+ | Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)| +-------------------------+----------+------+------+------------+-------------+ | clk_BUFGP | BUFGMUX7| No | 4 | 0.000 | 1.011 | +-------------------------+----------+------+------+------------+-------------+ Generating Pad Report. All signals are completely routed. Total REAL time to PAR completion: 4 secs Total CPU time to PAR completion: 1 secs Peak Memory Usage: 56 MB Placement: Completed - No errors found. Routing: Completed - No errors found. Writing design to file datapath.ncd. PAR done. Completed process "Place & Route". Started process "Generate Post-Place & Route Static Timing". Analysis completed Fri Mar 16 11:39:37 2007 -------------------------------------------------------------------------------- Generating Report ... Completed process "Generate Post-Place & Route Static Timing". Place & Route Module datapath . . . PAR command line: par -w -intstyle ise -ol std -t 1 datapath_map.ncd datapath.ncd datapath.pcf PAR completed successfully Started process "Generate Post-Place & Route Simulation Model". Completed process "Generate Post-Place & Route Simulation Model". Compiling vhdl file Z:/camurati/esercitazione_2/datapath.vhd in Library work. Entity (Architecture ) compiled. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file Z:/camurati/esercitazione_2/datapath.vhd in Library work. Entity (Architecture ) compiled. ========================================================================= * HDL Analysis * ========================================================================= Analyzing Entity (Architecture ). Entity analyzed. Unit generated. ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is Z:/camurati/esercitazione_2/datapath.vhd. Found 1-bit register for signal . Found 3-bit register for signal . Summary: inferred 4 D-type flip-flop(s). Unit synthesized. ========================================================================= * Advanced HDL Synthesis * ========================================================================= Advanced RAM inference ... Advanced multiplier inference ... Advanced Registered AddSub inference ... Dynamic shift register inference ... ========================================================================= HDL Synthesis Report Macro Statistics # Registers : 2 1-bit register : 1 3-bit register : 1 ========================================================================= ========================================================================= * Low Level Synthesis * ========================================================================= Optimizing unit ... Loading device for application Xst from file '3s200.nph' in environment C:/Program Files/Xilinx. Mapping all equations... Building and optimizing final netlist ... Found area constraint ratio of 100 (+ 5) on block datapath, actual ratio is 0. ========================================================================= * Final Report * ========================================================================= Device utilization summary: --------------------------- Selected Device : 3s200ft256-4 Number of Slices: 5 out of 1920 0% Number of Slice Flip Flops: 4 out of 3840 0% Number of 4 input LUTs: 9 out of 3840 0% Number of bonded IOBs: 10 out of 173 5% Number of GCLKs: 1 out of 8 12% ========================================================================= TIMING REPORT Clock Information: ------------------ -----------------------------------+------------------------+-------+ Clock Signal | Clock buffer(FF name) | Load | -----------------------------------+------------------------+-------+ clk | BUFGP | 4 | -----------------------------------+------------------------+-------+ Timing Summary: --------------- Speed Grade: -4 Minimum period: 1.939ns (Maximum Frequency: 515.730MHz) Minimum input arrival time before clock: 4.192ns Maximum output required time after clock: 6.060ns Maximum combinational path delay: No path found ========================================================================= Completed process "Synthesize". Started process "Translate". Command Line: ngdbuild -intstyle ise -dd z:\camurati\esercitazione_2/_ngo -i -p xc3s200-ft256-4 datapath.ngc datapath.ngd Reading NGO file "Z:/camurati/esercitazione_2/datapath.ngc" ... Reading component libraries for design expansion... Checking timing specifications ... Checking expanded design ... NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0 Total memory usage is 38140 kilobytes Writing NGD file "datapath.ngd" ... Writing NGDBUILD log file "datapath.bld"... NGDBUILD done. Completed process "Translate". Started process "Map". Using target part "3s200ft256-4". Removing unused or disabled logic... Running cover... Running directed packing... Running delay-based LUT packing... Running related packing... Design Summary: Number of errors: 0 Number of warnings: 0 Logic Utilization: Number of Slice Flip Flops: 4 out of 3,840 1% Number of 4 input LUTs: 9 out of 3,840 1% Logic Distribution: Number of occupied Slices: 5 out of 1,920 1% Number of Slices containing only related logic: 5 out of 5 100% Number of Slices containing unrelated logic: 0 out of 5 0% *See NOTES below for an explanation of the effects of unrelated logic Total Number of 4 input LUTs: 9 out of 3,840 1% Number of bonded IOBs: 11 out of 173 6% Number of GCLKs: 1 out of 8 12% Total equivalent gate count for design: 89 Additional JTAG gate count for IOBs: 528 Peak Memory Usage: 66 MB NOTES: Related logic is defined as being logic that shares connectivity - e.g. two LUTs are "related" if they share common inputs. When assembling slices, Map gives priority to combine logic that is related. Doing so results in the best timing performance. Unrelated logic shares no connectivity. Map will only begin packing unrelated logic into a slice once 99% of the slices are occupied through related logic packing. Note that once logic distribution reaches the 99% level through related logic packing, this does not mean the device is completely utilized. Unrelated logic packing will then begin, continuing until all usable LUTs and FFs are occupied. Depending on your timing budget, increased levels of unrelated logic packing may adversely affect the overall timing performance of your design. Mapping completed. See MAP report file "datapath_map.mrp" for details. Completed process "Map". Mapping Module datapath . . . MAP command line: map -intstyle ise -p xc3s200-ft256-4 -cm area -pr b -k 4 -c 100 -tx off -o datapath_map.ncd datapath.ngd datapath.pcf Mapping Module datapath: DONE Started process "Place & Route". Constraints file: datapath.pcf Loading device database for application Par from file "datapath_map.ncd". "datapath" is an NCD, version 2.38, device xc3s200, package ft256, speed -4 Loading device for application Par from file '3s200.nph' in environment C:/Program Files/Xilinx. Device speed data version: PRODUCTION 1.32 2004-06-25. Resolving physical constraints. Finished resolving physical constraints. Device utilization summary: Number of External IOBs 11 out of 173 6% Number of LOCed External IOBs 0 out of 11 0% Number of Slices 5 out of 1920 1% Number of BUFGMUXs 1 out of 8 12% Overall effort level (-ol): Standard (set by user) Placer effort level (-pl): Standard (set by user) Placer cost table entry (-t): 1 Router effort level (-rl): Standard (set by user) Phase 1.1 Phase 1.1 (Checksum:9896b2) REAL time: 0 secs Phase 3.3 Phase 3.3 (Checksum:1c9c37d) REAL time: 0 secs Phase 4.5 Phase 4.5 (Checksum:26259fc) REAL time: 0 secs Phase 5.8 . Phase 5.8 (Checksum:98ac2d) REAL time: 0 secs Phase 6.5 Phase 6.5 (Checksum:39386fa) REAL time: 0 secs Phase 7.18 Phase 7.18 (Checksum:42c1d79) REAL time: 0 secs Writing design to file datapath.ncd. Total REAL time to Placer completion: 0 secs Total CPU time to Placer completion: 0 secs Phase 1: 52 unrouted; REAL time: 0 secs Phase 2: 47 unrouted; REAL time: 0 secs Phase 3: 14 unrouted; REAL time: 0 secs Phase 4: 0 unrouted; REAL time: 0 secs Total REAL time to Router completion: 0 secs Total CPU time to Router completion: 0 secs Generating "par" statistics. ************************** Generating Clock Report ************************** +-------------------------+----------+------+------+------------+-------------+ | Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)| +-------------------------+----------+------+------+------------+-------------+ | clk_BUFGP | BUFGMUX7| No | 4 | 0.000 | 1.011 | +-------------------------+----------+------+------+------------+-------------+ Generating Pad Report. All signals are completely routed. Total REAL time to PAR completion: 4 secs Total CPU time to PAR completion: 1 secs Peak Memory Usage: 56 MB Placement: Completed - No errors found. Routing: Completed - No errors found. Writing design to file datapath.ncd. PAR done. Completed process "Place & Route". Started process "Generate Post-Place & Route Static Timing". Analysis completed Fri Mar 16 11:40:37 2007 -------------------------------------------------------------------------------- Generating Report ... Completed process "Generate Post-Place & Route Static Timing". Place & Route Module datapath . . . PAR command line: par -w -intstyle ise -ol std -t 1 datapath_map.ncd datapath.ncd datapath.pcf PAR completed successfully Started process "Generate Post-Place & Route Simulation Model". Completed process "Generate Post-Place & Route Simulation Model". Compiling vhdl file Z:/camurati/esercitazione_2/datapath.vhd in Library work. Entity (Architecture ) compiled. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file Z:/camurati/esercitazione_2/datapath.vhd in Library work. Entity (Architecture ) compiled. ========================================================================= * HDL Analysis * ========================================================================= Analyzing Entity (Architecture ). INFO:Xst:1304 - Contents of register in unit never changes during circuit operation. The register is replaced by logic. Entity analyzed. Unit generated. ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is Z:/camurati/esercitazione_2/datapath.vhd. Found 3-bit register for signal . Summary: inferred 3 D-type flip-flop(s). Unit synthesized. ========================================================================= * Advanced HDL Synthesis * ========================================================================= Advanced RAM inference ... Advanced multiplier inference ... Advanced Registered AddSub inference ... Dynamic shift register inference ... ========================================================================= HDL Synthesis Report Macro Statistics # Registers : 1 3-bit register : 1 ========================================================================= ========================================================================= * Low Level Synthesis * ========================================================================= Optimizing unit ... Loading device for application Xst from file '3s200.nph' in environment C:/Program Files/Xilinx. Mapping all equations... Building and optimizing final netlist ... Found area constraint ratio of 100 (+ 5) on block datapath, actual ratio is 0. ========================================================================= * Final Report * ========================================================================= Device utilization summary: --------------------------- Selected Device : 3s200ft256-4 Number of Slices: 4 out of 1920 0% Number of Slice Flip Flops: 3 out of 3840 0% Number of 4 input LUTs: 8 out of 3840 0% Number of bonded IOBs: 10 out of 173 5% Number of GCLKs: 1 out of 8 12% ========================================================================= TIMING REPORT Clock Information: ------------------ -----------------------------------+------------------------+-------+ Clock Signal | Clock buffer(FF name) | Load | -----------------------------------+------------------------+-------+ clk | BUFGP | 3 | -----------------------------------+------------------------+-------+ Timing Summary: --------------- Speed Grade: -4 Minimum period: 1.939ns (Maximum Frequency: 515.730MHz) Minimum input arrival time before clock: 4.163ns Maximum output required time after clock: 6.060ns Maximum combinational path delay: No path found ========================================================================= Completed process "Synthesize". Started process "Translate". Command Line: ngdbuild -intstyle ise -dd z:\camurati\esercitazione_2/_ngo -i -p xc3s200-ft256-4 datapath.ngc datapath.ngd Reading NGO file "Z:/camurati/esercitazione_2/datapath.ngc" ... Reading component libraries for design expansion... Checking timing specifications ... Checking expanded design ... NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0 Total memory usage is 38140 kilobytes Writing NGD file "datapath.ngd" ... Writing NGDBUILD log file "datapath.bld"... NGDBUILD done. Completed process "Translate". Started process "Map". Using target part "3s200ft256-4". Removing unused or disabled logic... Running cover... Running directed packing... Running delay-based LUT packing... Running related packing... Design Summary: Number of errors: 0 Number of warnings: 0 Logic Utilization: Number of Slice Flip Flops: 3 out of 3,840 1% Number of 4 input LUTs: 8 out of 3,840 1% Logic Distribution: Number of occupied Slices: 4 out of 1,920 1% Number of Slices containing only related logic: 4 out of 4 100% Number of Slices containing unrelated logic: 0 out of 4 0% *See NOTES below for an explanation of the effects of unrelated logic Total Number of 4 input LUTs: 8 out of 3,840 1% Number of bonded IOBs: 11 out of 173 6% Number of GCLKs: 1 out of 8 12% Total equivalent gate count for design: 75 Additional JTAG gate count for IOBs: 528 Peak Memory Usage: 66 MB NOTES: Related logic is defined as being logic that shares connectivity - e.g. two LUTs are "related" if they share common inputs. When assembling slices, Map gives priority to combine logic that is related. Doing so results in the best timing performance. Unrelated logic shares no connectivity. Map will only begin packing unrelated logic into a slice once 99% of the slices are occupied through related logic packing. Note that once logic distribution reaches the 99% level through related logic packing, this does not mean the device is completely utilized. Unrelated logic packing will then begin, continuing until all usable LUTs and FFs are occupied. Depending on your timing budget, increased levels of unrelated logic packing may adversely affect the overall timing performance of your design. Mapping completed. See MAP report file "datapath_map.mrp" for details. Completed process "Map". Mapping Module datapath . . . MAP command line: map -intstyle ise -p xc3s200-ft256-4 -cm area -pr b -k 4 -c 100 -tx off -o datapath_map.ncd datapath.ngd datapath.pcf Mapping Module datapath: DONE Started process "Place & Route". Constraints file: datapath.pcf Loading device database for application Par from file "datapath_map.ncd". "datapath" is an NCD, version 2.38, device xc3s200, package ft256, speed -4 Loading device for application Par from file '3s200.nph' in environment C:/Program Files/Xilinx. Device speed data version: PRODUCTION 1.32 2004-06-25. Resolving physical constraints. Finished resolving physical constraints. Device utilization summary: Number of External IOBs 11 out of 173 6% Number of LOCed External IOBs 0 out of 11 0% Number of Slices 4 out of 1920 1% Number of BUFGMUXs 1 out of 8 12% Overall effort level (-ol): Standard (set by user) Placer effort level (-pl): Standard (set by user) Placer cost table entry (-t): 1 Router effort level (-rl): Standard (set by user) Phase 1.1 Phase 1.1 (Checksum:9896af) REAL time: 0 secs Phase 3.3 Phase 3.3 (Checksum:1c9c37d) REAL time: 0 secs Phase 4.5 Phase 4.5 (Checksum:26259fc) REAL time: 0 secs Phase 5.8 . Phase 5.8 (Checksum:98b9a7) REAL time: 0 secs Phase 6.5 Phase 6.5 (Checksum:39386fa) REAL time: 0 secs Phase 7.18 Phase 7.18 (Checksum:42c1d79) REAL time: 0 secs Writing design to file datapath.ncd. Total REAL time to Placer completion: 0 secs Total CPU time to Placer completion: 0 secs Phase 1: 45 unrouted; REAL time: 0 secs Phase 2: 41 unrouted; REAL time: 0 secs Phase 3: 10 unrouted; REAL time: 0 secs Phase 4: 0 unrouted; REAL time: 0 secs Total REAL time to Router completion: 0 secs Total CPU time to Router completion: 0 secs Generating "par" statistics. ************************** Generating Clock Report ************************** +-------------------------+----------+------+------+------------+-------------+ | Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)| +-------------------------+----------+------+------+------------+-------------+ | clk_BUFGP | BUFGMUX7| No | 3 | 0.000 | 1.011 | +-------------------------+----------+------+------+------------+-------------+ Generating Pad Report. All signals are completely routed. Total REAL time to PAR completion: 4 secs Total CPU time to PAR completion: 1 secs Peak Memory Usage: 56 MB Placement: Completed - No errors found. Routing: Completed - No errors found. Writing design to file datapath.ncd. PAR done. Completed process "Place & Route". Started process "Generate Post-Place & Route Static Timing". Analysis completed Fri Mar 16 11:41:45 2007 -------------------------------------------------------------------------------- Generating Report ... Completed process "Generate Post-Place & Route Static Timing". Place & Route Module datapath . . . PAR command line: par -w -intstyle ise -ol std -t 1 datapath_map.ncd datapath.ncd datapath.pcf PAR completed successfully Started process "Generate Post-Place & Route Simulation Model". Completed process "Generate Post-Place & Route Simulation Model". Compiling vhdl file Z:/camurati/esercitazione_2/datapath.vhd in Library work. Entity (Architecture ) compiled. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file Z:/camurati/esercitazione_2/datapath.vhd in Library work. Entity (Architecture ) compiled. ========================================================================= * HDL Analysis * ========================================================================= Analyzing Entity (Architecture ). Entity analyzed. Unit generated. ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is Z:/camurati/esercitazione_2/datapath.vhd. Found 1-bit register for signal . Found 3-bit register for signal . Summary: inferred 4 D-type flip-flop(s). Unit synthesized. ========================================================================= * Advanced HDL Synthesis * ========================================================================= Advanced RAM inference ... Advanced multiplier inference ... Advanced Registered AddSub inference ... Dynamic shift register inference ... ========================================================================= HDL Synthesis Report Macro Statistics # Registers : 2 1-bit register : 1 3-bit register : 1 ========================================================================= ========================================================================= * Low Level Synthesis * ========================================================================= Optimizing unit ... Loading device for application Xst from file '3s200.nph' in environment C:/Program Files/Xilinx. Mapping all equations... Building and optimizing final netlist ... Found area constraint ratio of 100 (+ 5) on block datapath, actual ratio is 0. ========================================================================= * Final Report * ========================================================================= Device utilization summary: --------------------------- Selected Device : 3s200ft256-4 Number of Slices: 5 out of 1920 0% Number of Slice Flip Flops: 4 out of 3840 0% Number of 4 input LUTs: 9 out of 3840 0% Number of bonded IOBs: 10 out of 173 5% Number of GCLKs: 1 out of 8 12% ========================================================================= TIMING REPORT Clock Information: ------------------ -----------------------------------+------------------------+-------+ Clock Signal | Clock buffer(FF name) | Load | -----------------------------------+------------------------+-------+ clk | BUFGP | 4 | -----------------------------------+------------------------+-------+ Timing Summary: --------------- Speed Grade: -4 Minimum period: 1.939ns (Maximum Frequency: 515.730MHz) Minimum input arrival time before clock: 4.192ns Maximum output required time after clock: 6.060ns Maximum combinational path delay: No path found ========================================================================= Completed process "Synthesize". Started process "Translate". Command Line: ngdbuild -intstyle ise -dd z:\camurati\esercitazione_2/_ngo -i -p xc3s200-ft256-4 datapath.ngc datapath.ngd Reading NGO file "Z:/camurati/esercitazione_2/datapath.ngc" ... Reading component libraries for design expansion... Checking timing specifications ... Checking expanded design ... NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0 Total memory usage is 38140 kilobytes Writing NGD file "datapath.ngd" ... Writing NGDBUILD log file "datapath.bld"... NGDBUILD done. Completed process "Translate". Started process "Map". Using target part "3s200ft256-4". Removing unused or disabled logic... Running cover... Running directed packing... Running delay-based LUT packing... Running related packing... Design Summary: Number of errors: 0 Number of warnings: 0 Logic Utilization: Number of Slice Flip Flops: 4 out of 3,840 1% Number of 4 input LUTs: 9 out of 3,840 1% Logic Distribution: Number of occupied Slices: 5 out of 1,920 1% Number of Slices containing only related logic: 5 out of 5 100% Number of Slices containing unrelated logic: 0 out of 5 0% *See NOTES below for an explanation of the effects of unrelated logic Total Number of 4 input LUTs: 9 out of 3,840 1% Number of bonded IOBs: 11 out of 173 6% Number of GCLKs: 1 out of 8 12% Total equivalent gate count for design: 89 Additional JTAG gate count for IOBs: 528 Peak Memory Usage: 66 MB NOTES: Related logic is defined as being logic that shares connectivity - e.g. two LUTs are "related" if they share common inputs. When assembling slices, Map gives priority to combine logic that is related. Doing so results in the best timing performance. Unrelated logic shares no connectivity. Map will only begin packing unrelated logic into a slice once 99% of the slices are occupied through related logic packing. Note that once logic distribution reaches the 99% level through related logic packing, this does not mean the device is completely utilized. Unrelated logic packing will then begin, continuing until all usable LUTs and FFs are occupied. Depending on your timing budget, increased levels of unrelated logic packing may adversely affect the overall timing performance of your design. Mapping completed. See MAP report file "datapath_map.mrp" for details. Completed process "Map". Mapping Module datapath . . . MAP command line: map -intstyle ise -p xc3s200-ft256-4 -cm area -pr b -k 4 -c 100 -tx off -o datapath_map.ncd datapath.ngd datapath.pcf Mapping Module datapath: DONE Started process "Place & Route". Constraints file: datapath.pcf Loading device database for application Par from file "datapath_map.ncd". "datapath" is an NCD, version 2.38, device xc3s200, package ft256, speed -4 Loading device for application Par from file '3s200.nph' in environment C:/Program Files/Xilinx. Device speed data version: PRODUCTION 1.32 2004-06-25. Resolving physical constraints. Finished resolving physical constraints. Device utilization summary: Number of External IOBs 11 out of 173 6% Number of LOCed External IOBs 0 out of 11 0% Number of Slices 5 out of 1920 1% Number of BUFGMUXs 1 out of 8 12% Overall effort level (-ol): Standard (set by user) Placer effort level (-pl): Standard (set by user) Placer cost table entry (-t): 1 Router effort level (-rl): Standard (set by user) Phase 1.1 Phase 1.1 (Checksum:9896b2) REAL time: 0 secs Phase 3.3 Phase 3.3 (Checksum:1c9c37d) REAL time: 0 secs Phase 4.5 Phase 4.5 (Checksum:26259fc) REAL time: 0 secs Phase 5.8 . Phase 5.8 (Checksum:98ac2d) REAL time: 0 secs Phase 6.5 Phase 6.5 (Checksum:39386fa) REAL time: 0 secs Phase 7.18 Phase 7.18 (Checksum:42c1d79) REAL time: 0 secs Writing design to file datapath.ncd. Total REAL time to Placer completion: 0 secs Total CPU time to Placer completion: 0 secs Phase 1: 52 unrouted; REAL time: 0 secs Phase 2: 47 unrouted; REAL time: 0 secs Phase 3: 14 unrouted; REAL time: 0 secs Phase 4: 0 unrouted; REAL time: 0 secs Total REAL time to Router completion: 0 secs Total CPU time to Router completion: 0 secs Generating "par" statistics. ************************** Generating Clock Report ************************** +-------------------------+----------+------+------+------------+-------------+ | Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)| +-------------------------+----------+------+------+------------+-------------+ | clk_BUFGP | BUFGMUX7| No | 4 | 0.000 | 1.011 | +-------------------------+----------+------+------+------------+-------------+ Generating Pad Report. All signals are completely routed. Total REAL time to PAR completion: 4 secs Total CPU time to PAR completion: 1 secs Peak Memory Usage: 56 MB Placement: Completed - No errors found. Routing: Completed - No errors found. Writing design to file datapath.ncd. PAR done. Completed process "Place & Route". Started process "Generate Post-Place & Route Static Timing". Analysis completed Fri Mar 16 11:42:37 2007 -------------------------------------------------------------------------------- Generating Report ... Completed process "Generate Post-Place & Route Static Timing". Place & Route Module datapath . . . PAR command line: par -w -intstyle ise -ol std -t 1 datapath_map.ncd datapath.ncd datapath.pcf PAR completed successfully Started process "Generate Post-Place & Route Simulation Model". Completed process "Generate Post-Place & Route Simulation Model". Compiling vhdl file Z:/camurati/esercitazione_2/datapath.vhd in Library work. Entity (Architecture ) compiled. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file Z:/camurati/esercitazione_2/datapath.vhd in Library work. Entity (Architecture ) compiled. ========================================================================= * HDL Analysis * ========================================================================= Analyzing Entity (Architecture ). Entity analyzed. Unit generated. ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is Z:/camurati/esercitazione_2/datapath.vhd. Found 1-bit register for signal . Found 3-bit register for signal . Summary: inferred 4 D-type flip-flop(s). Unit synthesized. ========================================================================= * Advanced HDL Synthesis * ========================================================================= Advanced RAM inference ... Advanced multiplier inference ... Advanced Registered AddSub inference ... Dynamic shift register inference ... ========================================================================= HDL Synthesis Report Macro Statistics # Registers : 2 1-bit register : 1 3-bit register : 1 ========================================================================= ========================================================================= * Low Level Synthesis * ========================================================================= Optimizing unit ... Loading device for application Xst from file '3s200.nph' in environment C:/Program Files/Xilinx. Mapping all equations... Building and optimizing final netlist ... Found area constraint ratio of 100 (+ 5) on block datapath, actual ratio is 0. ========================================================================= * Final Report * ========================================================================= Device utilization summary: --------------------------- Selected Device : 3s200ft256-4 Number of Slices: 5 out of 1920 0% Number of Slice Flip Flops: 4 out of 3840 0% Number of 4 input LUTs: 9 out of 3840 0% Number of bonded IOBs: 10 out of 173 5% Number of GCLKs: 1 out of 8 12% ========================================================================= TIMING REPORT Clock Information: ------------------ -----------------------------------+------------------------+-------+ Clock Signal | Clock buffer(FF name) | Load | -----------------------------------+------------------------+-------+ clk | BUFGP | 4 | -----------------------------------+------------------------+-------+ Timing Summary: --------------- Speed Grade: -4 Minimum period: 1.939ns (Maximum Frequency: 515.730MHz) Minimum input arrival time before clock: 4.192ns Maximum output required time after clock: 6.060ns Maximum combinational path delay: No path found ========================================================================= Completed process "Synthesize". Started process "Translate". Command Line: ngdbuild -intstyle ise -dd z:\camurati\esercitazione_2/_ngo -i -p xc3s200-ft256-4 datapath.ngc datapath.ngd Reading NGO file "Z:/camurati/esercitazione_2/datapath.ngc" ... Reading component libraries for design expansion... Checking timing specifications ... Checking expanded design ... NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0 Total memory usage is 38140 kilobytes Writing NGD file "datapath.ngd" ... Writing NGDBUILD log file "datapath.bld"... NGDBUILD done. Completed process "Translate". Started process "Map". Using target part "3s200ft256-4". Removing unused or disabled logic... Running cover... Running directed packing... Running delay-based LUT packing... Running related packing... Design Summary: Number of errors: 0 Number of warnings: 0 Logic Utilization: Number of Slice Flip Flops: 4 out of 3,840 1% Number of 4 input LUTs: 9 out of 3,840 1% Logic Distribution: Number of occupied Slices: 5 out of 1,920 1% Number of Slices containing only related logic: 5 out of 5 100% Number of Slices containing unrelated logic: 0 out of 5 0% *See NOTES below for an explanation of the effects of unrelated logic Total Number of 4 input LUTs: 9 out of 3,840 1% Number of bonded IOBs: 11 out of 173 6% Number of GCLKs: 1 out of 8 12% Total equivalent gate count for design: 89 Additional JTAG gate count for IOBs: 528 Peak Memory Usage: 66 MB NOTES: Related logic is defined as being logic that shares connectivity - e.g. two LUTs are "related" if they share common inputs. When assembling slices, Map gives priority to combine logic that is related. Doing so results in the best timing performance. Unrelated logic shares no connectivity. Map will only begin packing unrelated logic into a slice once 99% of the slices are occupied through related logic packing. Note that once logic distribution reaches the 99% level through related logic packing, this does not mean the device is completely utilized. Unrelated logic packing will then begin, continuing until all usable LUTs and FFs are occupied. Depending on your timing budget, increased levels of unrelated logic packing may adversely affect the overall timing performance of your design. Mapping completed. See MAP report file "datapath_map.mrp" for details. Completed process "Map". Mapping Module datapath . . . MAP command line: map -intstyle ise -p xc3s200-ft256-4 -cm area -pr b -k 4 -c 100 -tx off -o datapath_map.ncd datapath.ngd datapath.pcf Mapping Module datapath: DONE Started process "Place & Route". Constraints file: datapath.pcf Loading device database for application Par from file "datapath_map.ncd". "datapath" is an NCD, version 2.38, device xc3s200, package ft256, speed -4 Loading device for application Par from file '3s200.nph' in environment C:/Program Files/Xilinx. Device speed data version: PRODUCTION 1.32 2004-06-25. Resolving physical constraints. Finished resolving physical constraints. Device utilization summary: Number of External IOBs 11 out of 173 6% Number of LOCed External IOBs 0 out of 11 0% Number of Slices 5 out of 1920 1% Number of BUFGMUXs 1 out of 8 12% Overall effort level (-ol): Standard (set by user) Placer effort level (-pl): Standard (set by user) Placer cost table entry (-t): 1 Router effort level (-rl): Standard (set by user) Phase 1.1 Phase 1.1 (Checksum:9896b2) REAL time: 0 secs Phase 3.3 Phase 3.3 (Checksum:1c9c37d) REAL time: 0 secs Phase 4.5 Phase 4.5 (Checksum:26259fc) REAL time: 0 secs Phase 5.8 . Phase 5.8 (Checksum:98ac2d) REAL time: 0 secs Phase 6.5 Phase 6.5 (Checksum:39386fa) REAL time: 0 secs Phase 7.18 Phase 7.18 (Checksum:42c1d79) REAL time: 0 secs Writing design to file datapath.ncd. Total REAL time to Placer completion: 0 secs Total CPU time to Placer completion: 0 secs Phase 1: 52 unrouted; REAL time: 0 secs Phase 2: 47 unrouted; REAL time: 0 secs Phase 3: 14 unrouted; REAL time: 0 secs Phase 4: 0 unrouted; REAL time: 0 secs Total REAL time to Router completion: 0 secs Total CPU time to Router completion: 0 secs Generating "par" statistics. ************************** Generating Clock Report ************************** +-------------------------+----------+------+------+------------+-------------+ | Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)| +-------------------------+----------+------+------+------------+-------------+ | clk_BUFGP | BUFGMUX7| No | 4 | 0.000 | 1.011 | +-------------------------+----------+------+------+------------+-------------+ Generating Pad Report. All signals are completely routed. Total REAL time to PAR completion: 4 secs Total CPU time to PAR completion: 1 secs Peak Memory Usage: 56 MB Placement: Completed - No errors found. Routing: Completed - No errors found. Writing design to file datapath.ncd. PAR done. Completed process "Place & Route". Started process "Generate Post-Place & Route Static Timing". Analysis completed Fri Mar 16 11:43:41 2007 -------------------------------------------------------------------------------- Generating Report ... Completed process "Generate Post-Place & Route Static Timing". Place & Route Module datapath . . . PAR command line: par -w -intstyle ise -ol std -t 1 datapath_map.ncd datapath.ncd datapath.pcf PAR completed successfully Started process "Generate Post-Place & Route Simulation Model". Completed process "Generate Post-Place & Route Simulation Model". Compiling vhdl file Z:/camurati/esercitazione_2/datapath.vhd in Library work. Entity (Architecture ) compiled. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file Z:/camurati/esercitazione_2/datapath.vhd in Library work. Entity (Architecture ) compiled. ========================================================================= * HDL Analysis * ========================================================================= Analyzing Entity (Architecture ). Entity analyzed. Unit generated. ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is Z:/camurati/esercitazione_2/datapath.vhd. Found 1-bit register for signal . Found 3-bit register for signal . Summary: inferred 4 D-type flip-flop(s). Unit synthesized. ========================================================================= * Advanced HDL Synthesis * ========================================================================= Advanced RAM inference ... Advanced multiplier inference ... Advanced Registered AddSub inference ... Dynamic shift register inference ... ========================================================================= HDL Synthesis Report Macro Statistics # Registers : 2 1-bit register : 1 3-bit register : 1 ========================================================================= ========================================================================= * Low Level Synthesis * ========================================================================= Optimizing unit ... Loading device for application Xst from file '3s200.nph' in environment C:/Program Files/Xilinx. Mapping all equations... Building and optimizing final netlist ... Found area constraint ratio of 100 (+ 5) on block datapath, actual ratio is 0. ========================================================================= * Final Report * ========================================================================= Device utilization summary: --------------------------- Selected Device : 3s200ft256-4 Number of Slices: 5 out of 1920 0% Number of Slice Flip Flops: 4 out of 3840 0% Number of 4 input LUTs: 9 out of 3840 0% Number of bonded IOBs: 10 out of 173 5% Number of GCLKs: 1 out of 8 12% ========================================================================= TIMING REPORT Clock Information: ------------------ -----------------------------------+------------------------+-------+ Clock Signal | Clock buffer(FF name) | Load | -----------------------------------+------------------------+-------+ clk | BUFGP | 4 | -----------------------------------+------------------------+-------+ Timing Summary: --------------- Speed Grade: -4 Minimum period: 1.939ns (Maximum Frequency: 515.730MHz) Minimum input arrival time before clock: 4.192ns Maximum output required time after clock: 6.060ns Maximum combinational path delay: No path found ========================================================================= Completed process "Synthesize". Started process "Translate". Command Line: ngdbuild -intstyle ise -dd z:\camurati\esercitazione_2/_ngo -i -p xc3s200-ft256-4 datapath.ngc datapath.ngd Reading NGO file "Z:/camurati/esercitazione_2/datapath.ngc" ... Reading component libraries for design expansion... Checking timing specifications ... Checking expanded design ... NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0 Total memory usage is 38140 kilobytes Writing NGD file "datapath.ngd" ... Writing NGDBUILD log file "datapath.bld"... NGDBUILD done. Completed process "Translate". Started process "Map". Using target part "3s200ft256-4". Removing unused or disabled logic... Running cover... Running directed packing... Running delay-based LUT packing... Running related packing... Design Summary: Number of errors: 0 Number of warnings: 0 Logic Utilization: Number of Slice Flip Flops: 4 out of 3,840 1% Number of 4 input LUTs: 9 out of 3,840 1% Logic Distribution: Number of occupied Slices: 5 out of 1,920 1% Number of Slices containing only related logic: 5 out of 5 100% Number of Slices containing unrelated logic: 0 out of 5 0% *See NOTES below for an explanation of the effects of unrelated logic Total Number of 4 input LUTs: 9 out of 3,840 1% Number of bonded IOBs: 11 out of 173 6% Number of GCLKs: 1 out of 8 12% Total equivalent gate count for design: 89 Additional JTAG gate count for IOBs: 528 Peak Memory Usage: 66 MB NOTES: Related logic is defined as being logic that shares connectivity - e.g. two LUTs are "related" if they share common inputs. When assembling slices, Map gives priority to combine logic that is related. Doing so results in the best timing performance. Unrelated logic shares no connectivity. Map will only begin packing unrelated logic into a slice once 99% of the slices are occupied through related logic packing. Note that once logic distribution reaches the 99% level through related logic packing, this does not mean the device is completely utilized. Unrelated logic packing will then begin, continuing until all usable LUTs and FFs are occupied. Depending on your timing budget, increased levels of unrelated logic packing may adversely affect the overall timing performance of your design. Mapping completed. See MAP report file "datapath_map.mrp" for details. Completed process "Map". Mapping Module datapath . . . MAP command line: map -intstyle ise -p xc3s200-ft256-4 -cm area -pr b -k 4 -c 100 -tx off -o datapath_map.ncd datapath.ngd datapath.pcf Mapping Module datapath: DONE Started process "Place & Route". Constraints file: datapath.pcf Loading device database for application Par from file "datapath_map.ncd". "datapath" is an NCD, version 2.38, device xc3s200, package ft256, speed -4 Loading device for application Par from file '3s200.nph' in environment C:/Program Files/Xilinx. Device speed data version: PRODUCTION 1.32 2004-06-25. Resolving physical constraints. Finished resolving physical constraints. Device utilization summary: Number of External IOBs 11 out of 173 6% Number of LOCed External IOBs 0 out of 11 0% Number of Slices 5 out of 1920 1% Number of BUFGMUXs 1 out of 8 12% Overall effort level (-ol): Standard (set by user) Placer effort level (-pl): Standard (set by user) Placer cost table entry (-t): 1 Router effort level (-rl): Standard (set by user) Phase 1.1 Phase 1.1 (Checksum:9896b2) REAL time: 0 secs Phase 3.3 Phase 3.3 (Checksum:1c9c37d) REAL time: 0 secs Phase 4.5 Phase 4.5 (Checksum:26259fc) REAL time: 0 secs Phase 5.8 . Phase 5.8 (Checksum:98ac2d) REAL time: 0 secs Phase 6.5 Phase 6.5 (Checksum:39386fa) REAL time: 0 secs Phase 7.18 Phase 7.18 (Checksum:42c1d79) REAL time: 0 secs Writing design to file datapath.ncd. Total REAL time to Placer completion: 0 secs Total CPU time to Placer completion: 0 secs Phase 1: 52 unrouted; REAL time: 0 secs Phase 2: 47 unrouted; REAL time: 0 secs Phase 3: 14 unrouted; REAL time: 0 secs Phase 4: 0 unrouted; REAL time: 0 secs Total REAL time to Router completion: 0 secs Total CPU time to Router completion: 0 secs Generating "par" statistics. ************************** Generating Clock Report ************************** +-------------------------+----------+------+------+------------+-------------+ | Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)| +-------------------------+----------+------+------+------------+-------------+ | clk_BUFGP | BUFGMUX7| No | 4 | 0.000 | 1.011 | +-------------------------+----------+------+------+------------+-------------+ Generating Pad Report. All signals are completely routed. Total REAL time to PAR completion: 4 secs Total CPU time to PAR completion: 1 secs Peak Memory Usage: 56 MB Placement: Completed - No errors found. Routing: Completed - No errors found. Writing design to file datapath.ncd. PAR done. Completed process "Place & Route". Started process "Generate Post-Place & Route Static Timing". Analysis completed Fri Mar 16 11:45:53 2007 -------------------------------------------------------------------------------- Generating Report ... Completed process "Generate Post-Place & Route Static Timing". Place & Route Module datapath . . . PAR command line: par -w -intstyle ise -ol std -t 1 datapath_map.ncd datapath.ncd datapath.pcf PAR completed successfully Started process "Generate Post-Place & Route Simulation Model". Completed process "Generate Post-Place & Route Simulation Model". Compiling vhdl file Z:/camurati/esercitazione_2/datapath.vhd in Library work. Entity (Architecture ) compiled. Project Navigator Auto-Make Log File ------------------------------------- Started process "View VHDL Functional Model". Release 6.3i - sch2vhdl G.35 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. DRC Check completed: No Error found. Vhdl netlist file generated. Completed process "View VHDL Functional Model". Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file Z:/camurati/esercitazione_2/datapath.vhd in Library work. Architecture behavioral of Entity datapath is up to date. Compiling vhdl file Z:/camurati/esercitazione_2/next_state_logic.vhd in Library work. Architecture behavioral of Entity next_state_logic is up to date. Compiling vhdl file Z:/camurati/esercitazione_2/riconoscitore_1011.vhf in Library work. Entity (Architecture ) compiled. ========================================================================= * HDL Analysis * ========================================================================= Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is Z:/camurati/esercitazione_2/next_state_logic.vhd. Found 3-bit register for signal . Summary: inferred 3 D-type flip-flop(s). Unit synthesized. Synthesizing Unit . Related source file is Z:/camurati/esercitazione_2/datapath.vhd. Found 1-bit register for signal . Found 3-bit register for signal . Summary: inferred 4 D-type flip-flop(s). Unit synthesized. Synthesizing Unit . Related source file is Z:/camurati/esercitazione_2/riconoscitore_1011.vhf. Unit synthesized. ========================================================================= * Advanced HDL Synthesis * ========================================================================= Advanced RAM inference ... Advanced multiplier inference ... Advanced Registered AddSub inference ... Dynamic shift register inference ... ========================================================================= HDL Synthesis Report Macro Statistics # Registers : 3 1-bit register : 1 3-bit register : 2 ========================================================================= ========================================================================= * Low Level Synthesis * ========================================================================= Optimizing unit ... Optimizing unit ... Loading device for application Xst from file '3s200.nph' in environment C:/Program Files/Xilinx. Mapping all equations... Building and optimizing final netlist ... Found area constraint ratio of 100 (+ 5) on block riconoscitore_1011, actual ratio is 0. ========================================================================= * Final Report * ========================================================================= Device utilization summary: --------------------------- Selected Device : 3s200ft256-4 Number of Slices: 5 out of 1920 0% Number of Slice Flip Flops: 7 out of 3840 0% Number of 4 input LUTs: 7 out of 3840 0% Number of bonded IOBs: 7 out of 173 4% Number of GCLKs: 1 out of 8 12% ========================================================================= TIMING REPORT Clock Information: ------------------ -----------------------------------+------------------------+-------+ Clock Signal | Clock buffer(FF name) | Load | -----------------------------------+------------------------+-------+ Clock | BUFGP | 7 | -----------------------------------+------------------------+-------+ Timing Summary: --------------- Speed Grade: -4 Minimum period: 2.581ns (Maximum Frequency: 387.447MHz) Minimum input arrival time before clock: 3.732ns Maximum output required time after clock: 6.342ns Maximum combinational path delay: No path found ========================================================================= Completed process "Synthesize". Started process "Translate". Command Line: ngdbuild -intstyle ise -dd z:\camurati\esercitazione_2/_ngo -i -p xc3s200-ft256-4 riconoscitore_1011.ngc riconoscitore_1011.ngd Reading NGO file "Z:/camurati/esercitazione_2/riconoscitore_1011.ngc" ... Reading component libraries for design expansion... Checking timing specifications ... Checking expanded design ... NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0 Total memory usage is 38140 kilobytes Writing NGD file "riconoscitore_1011.ngd" ... Writing NGDBUILD log file "riconoscitore_1011.bld"... NGDBUILD done. Completed process "Translate". Started process "Map". Using target part "3s200ft256-4". Removing unused or disabled logic... Running cover... Running directed packing... Running delay-based LUT packing... Running related packing... Design Summary: Number of errors: 0 Number of warnings: 0 Logic Utilization: Number of Slice Flip Flops: 7 out of 3,840 1% Number of 4 input LUTs: 7 out of 3,840 1% Logic Distribution: Number of occupied Slices: 6 out of 1,920 1% Number of Slices containing only related logic: 6 out of 6 100% Number of Slices containing unrelated logic: 0 out of 6 0% *See NOTES below for an explanation of the effects of unrelated logic Total Number of 4 input LUTs: 7 out of 3,840 1% Number of bonded IOBs: 8 out of 173 4% Number of GCLKs: 1 out of 8 12% Total equivalent gate count for design: 110 Additional JTAG gate count for IOBs: 384 Peak Memory Usage: 66 MB NOTES: Related logic is defined as being logic that shares connectivity - e.g. two LUTs are "related" if they share common inputs. When assembling slices, Map gives priority to combine logic that is related. Doing so results in the best timing performance. Unrelated logic shares no connectivity. Map will only begin packing unrelated logic into a slice once 99% of the slices are occupied through related logic packing. Note that once logic distribution reaches the 99% level through related logic packing, this does not mean the device is completely utilized. Unrelated logic packing will then begin, continuing until all usable LUTs and FFs are occupied. Depending on your timing budget, increased levels of unrelated logic packing may adversely affect the overall timing performance of your design. Mapping completed. See MAP report file "riconoscitore_1011_map.mrp" for details. Completed process "Map". Mapping Module riconoscitore_1011 . . . MAP command line: map -intstyle ise -p xc3s200-ft256-4 -cm area -pr b -k 4 -c 100 -tx off -o riconoscitore_1011_map.ncd riconoscitore_1011.ngd riconoscitore_1011.pcf Mapping Module riconoscitore_1011: DONE Started process "Place & Route". Constraints file: riconoscitore_1011.pcf Loading device database for application Par from file "riconoscitore_1011_map.ncd". "riconoscitore_1011" is an NCD, version 2.38, device xc3s200, package ft256, speed -4 Loading device for application Par from file '3s200.nph' in environment C:/Program Files/Xilinx. Device speed data version: PRODUCTION 1.32 2004-06-25. Resolving physical constraints. Finished resolving physical constraints. Device utilization summary: Number of External IOBs 8 out of 173 4% Number of LOCed External IOBs 0 out of 8 0% Number of Slices 6 out of 1920 1% Number of BUFGMUXs 1 out of 8 12% Overall effort level (-ol): Standard (set by user) Placer effort level (-pl): Standard (set by user) Placer cost table entry (-t): 1 Router effort level (-rl): Standard (set by user) Phase 1.1 Phase 1.1 (Checksum:9896ac) REAL time: 0 secs Phase 3.3 Phase 3.3 (Checksum:1c9c37d) REAL time: 0 secs Phase 4.5 Phase 4.5 (Checksum:26259fc) REAL time: 0 secs Phase 5.8 . Phase 5.8 (Checksum:98a570) REAL time: 0 secs Phase 6.5 Phase 6.5 (Checksum:39386fa) REAL time: 0 secs Phase 7.18 Phase 7.18 (Checksum:42c1d79) REAL time: 0 secs Writing design to file riconoscitore_1011.ncd. Total REAL time to Placer completion: 0 secs Total CPU time to Placer completion: 0 secs Phase 1: 56 unrouted; REAL time: 0 secs Phase 2: 49 unrouted; REAL time: 0 secs Phase 3: 17 unrouted; REAL time: 0 secs Phase 4: 0 unrouted; REAL time: 0 secs Total REAL time to Router completion: 0 secs Total CPU time to Router completion: 0 secs Generating "par" statistics. ************************** Generating Clock Report ************************** +-------------------------+----------+------+------+------------+-------------+ | Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)| +-------------------------+----------+------+------+------------+-------------+ | Clock_BUFGP | BUFGMUX7| No | 6 | 0.000 | 1.011 | +-------------------------+----------+------+------+------------+-------------+ Generating Pad Report. All signals are completely routed. Total REAL time to PAR completion: 4 secs Total CPU time to PAR completion: 1 secs Peak Memory Usage: 56 MB Placement: Completed - No errors found. Routing: Completed - No errors found. Writing design to file riconoscitore_1011.ncd. PAR done. Completed process "Place & Route". Started process "Generate Post-Place & Route Static Timing". Analysis completed Fri Mar 16 11:47:03 2007 -------------------------------------------------------------------------------- Generating Report ... Completed process "Generate Post-Place & Route Static Timing". Place & Route Module riconoscitore_1011 . . . PAR command line: par -w -intstyle ise -ol std -t 1 riconoscitore_1011_map.ncd riconoscitore_1011.ncd riconoscitore_1011.pcf PAR completed successfully Started process "Generate Post-Place & Route Simulation Model". Completed process "Generate Post-Place & Route Simulation Model". Compiling vhdl file Z:/camurati/esercitazione_2/riconoscitore_1011.vhf in Library work. Entity (Architecture ) compiled. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file Z:/camurati/esercitazione_2/next_state_logic.vhd in Library work. Architecture behavioral of Entity next_state_logic is up to date. ========================================================================= * HDL Analysis * ========================================================================= Analyzing Entity (Architecture ). Entity analyzed. Unit generated. ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is Z:/camurati/esercitazione_2/next_state_logic.vhd. Found 3-bit register for signal . Summary: inferred 3 D-type flip-flop(s). Unit synthesized. ========================================================================= * Advanced HDL Synthesis * ========================================================================= Advanced RAM inference ... Advanced multiplier inference ... Advanced Registered AddSub inference ... Dynamic shift register inference ... ========================================================================= HDL Synthesis Report Macro Statistics # Registers : 1 3-bit register : 1 ========================================================================= ========================================================================= * Low Level Synthesis * ========================================================================= Optimizing unit ... Loading device for application Xst from file '3s200.nph' in environment C:/Program Files/Xilinx. Mapping all equations... Building and optimizing final netlist ... Found area constraint ratio of 100 (+ 5) on block next_state_logic, actual ratio is 0. ========================================================================= * Final Report * ========================================================================= Device utilization summary: --------------------------- Selected Device : 3s200ft256-4 Number of Slices: 2 out of 1920 0% Number of Slice Flip Flops: 3 out of 3840 0% Number of bonded IOBs: 7 out of 173 4% Number of GCLKs: 1 out of 8 12% ========================================================================= TIMING REPORT Clock Information: ------------------ -----------------------------------+------------------------+-------+ Clock Signal | Clock buffer(FF name) | Load | -----------------------------------+------------------------+-------+ clk | BUFGP | 3 | -----------------------------------+------------------------+-------+ Timing Summary: --------------- Speed Grade: -4 Minimum period: No path found Minimum input arrival time before clock: 3.533ns Maximum output required time after clock: 5.835ns Maximum combinational path delay: No path found ========================================================================= Completed process "Synthesize". Started process "Translate". Command Line: ngdbuild -intstyle ise -dd z:\camurati\esercitazione_2/_ngo -i -p xc3s200-ft256-4 next_state_logic.ngc next_state_logic.ngd Reading NGO file "Z:/camurati/esercitazione_2/next_state_logic.ngc" ... Reading component libraries for design expansion... Checking timing specifications ... Checking expanded design ... NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0 Total memory usage is 38140 kilobytes Writing NGD file "next_state_logic.ngd" ... Writing NGDBUILD log file "next_state_logic.bld"... NGDBUILD done. Completed process "Translate". Started process "Map". Using target part "3s200ft256-4". Removing unused or disabled logic... Running cover... Running directed packing... Running delay-based LUT packing... Running related packing... Design Summary: Number of errors: 0 Number of warnings: 0 Logic Utilization: Logic Distribution: Number of Slices containing only related logic: 0 out of 0 0% Number of Slices containing unrelated logic: 0 out of 0 0% *See NOTES below for an explanation of the effects of unrelated logic Number of bonded IOBs: 8 out of 173 4% IOB Flip Flops: 3 Number of GCLKs: 1 out of 8 12% Total equivalent gate count for design: 27 Additional JTAG gate count for IOBs: 384 Peak Memory Usage: 66 MB NOTES: Related logic is defined as being logic that shares connectivity - e.g. two LUTs are "related" if they share common inputs. When assembling slices, Map gives priority to combine logic that is related. Doing so results in the best timing performance. Unrelated logic shares no connectivity. Map will only begin packing unrelated logic into a slice once 99% of the slices are occupied through related logic packing. Note that once logic distribution reaches the 99% level through related logic packing, this does not mean the device is completely utilized. Unrelated logic packing will then begin, continuing until all usable LUTs and FFs are occupied. Depending on your timing budget, increased levels of unrelated logic packing may adversely affect the overall timing performance of your design. Mapping completed. See MAP report file "next_state_logic_map.mrp" for details. Completed process "Map". Mapping Module next_state_logic . . . MAP command line: map -intstyle ise -p xc3s200-ft256-4 -cm area -pr b -k 4 -c 100 -tx off -o next_state_logic_map.ncd next_state_logic.ngd next_state_logic.pcf Mapping Module next_state_logic: DONE Started process "Place & Route". Constraints file: next_state_logic.pcf Loading device database for application Par from file "next_state_logic_map.ncd". "next_state_logic" is an NCD, version 2.38, device xc3s200, package ft256, speed -4 Loading device for application Par from file '3s200.nph' in environment C:/Program Files/Xilinx. Device speed data version: PRODUCTION 1.32 2004-06-25. Resolving physical constraints. Finished resolving physical constraints. Device utilization summary: Number of External IOBs 8 out of 173 4% Number of LOCed External IOBs 0 out of 8 0% Number of BUFGMUXs 1 out of 8 12% Overall effort level (-ol): Standard (set by user) Placer effort level (-pl): Standard (set by user) Placer cost table entry (-t): 1 Router effort level (-rl): Standard (set by user) Phase 1.1 Phase 1.1 (Checksum:989691) REAL time: 0 secs . Phase 3.3 Phase 3.3 (Checksum:1c9c37d) REAL time: 0 secs Phase 4.5 Phase 4.5 (Checksum:26259fc) REAL time: 0 secs Phase 5.8 Phase 5.8 (Checksum:98b3cb) REAL time: 0 secs Phase 6.5 Phase 6.5 (Checksum:39386fa) REAL time: 0 secs Phase 7.18 Phase 7.18 (Checksum:42c1d79) REAL time: 0 secs Writing design to file next_state_logic.ncd. Total REAL time to Placer completion: 0 secs Total CPU time to Placer completion: 0 secs Phase 1: 11 unrouted; REAL time: 0 secs Phase 2: 7 unrouted; REAL time: 0 secs Phase 3: 0 unrouted; REAL time: 0 secs Phase 4: 0 unrouted; REAL time: 0 secs Total REAL time to Router completion: 0 secs Total CPU time to Router completion: 0 secs Generating "par" statistics. ************************** Generating Clock Report ************************** +-------------------------+----------+------+------+------------+-------------+ | Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)| +-------------------------+----------+------+------+------------+-------------+ | clk_BUFGP | BUFGMUX3| No | 3 | 0.001 | 1.051 | +-------------------------+----------+------+------+------------+-------------+ Generating Pad Report. All signals are completely routed. Total REAL time to PAR completion: 4 secs Total CPU time to PAR completion: 1 secs Peak Memory Usage: 55 MB Placement: Completed - No errors found. Routing: Completed - No errors found. Writing design to file next_state_logic.ncd. PAR done. Completed process "Place & Route". Started process "Generate Post-Place & Route Static Timing". Analysis completed Fri Mar 16 11:50:09 2007 -------------------------------------------------------------------------------- Generating Report ... Completed process "Generate Post-Place & Route Static Timing". Place & Route Module next_state_logic . . . PAR command line: par -w -intstyle ise -ol std -t 1 next_state_logic_map.ncd next_state_logic.ncd next_state_logic.pcf PAR completed successfully Started process "Generate Post-Place & Route Simulation Model". Completed process "Generate Post-Place & Route Simulation Model". Compiling vhdl file Z:/camurati/esercitazione_2/next_state_logic.vhd in Library work. Entity (Architecture ) compiled. Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file Z:/camurati/esercitazione_2/next_state_logic.vhd in Library work. Entity (Architecture ) compiled. ========================================================================= * HDL Analysis * ========================================================================= Analyzing Entity (Architecture ). Entity analyzed. Unit generated. ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is Z:/camurati/esercitazione_2/next_state_logic.vhd. Found 3-bit register for signal . Summary: inferred 3 D-type flip-flop(s). Unit synthesized. ========================================================================= * Advanced HDL Synthesis * ========================================================================= Advanced RAM inference ... Advanced multiplier inference ... Advanced Registered AddSub inference ... Dynamic shift register inference ... ========================================================================= HDL Synthesis Report Macro Statistics # Registers : 1 3-bit register : 1 ========================================================================= ========================================================================= * Low Level Synthesis * ========================================================================= Optimizing unit ... Loading device for application Xst from file '3s200.nph' in environment C:/Program Files/Xilinx. Mapping all equations... Building and optimizing final netlist ... Found area constraint ratio of 100 (+ 5) on block next_state_logic, actual ratio is 0. ========================================================================= * Final Report * ========================================================================= Device utilization summary: --------------------------- Selected Device : 3s200ft256-4 Number of Slices: 2 out of 1920 0% Number of Slice Flip Flops: 3 out of 3840 0% Number of bonded IOBs: 7 out of 173 4% Number of GCLKs: 1 out of 8 12% ========================================================================= TIMING REPORT Clock Information: ------------------ -----------------------------------+------------------------+-------+ Clock Signal | Clock buffer(FF name) | Load | -----------------------------------+------------------------+-------+ clk | BUFGP | 3 | -----------------------------------+------------------------+-------+ Timing Summary: --------------- Speed Grade: -4 Minimum period: No path found Minimum input arrival time before clock: 3.533ns Maximum output required time after clock: 5.835ns Maximum combinational path delay: No path found ========================================================================= Completed process "Synthesize". Started process "Translate". Command Line: ngdbuild -intstyle ise -dd z:\camurati\esercitazione_2/_ngo -i -p xc3s200-ft256-4 next_state_logic.ngc next_state_logic.ngd Reading NGO file "Z:/camurati/esercitazione_2/next_state_logic.ngc" ... Reading component libraries for design expansion... Checking timing specifications ... Checking expanded design ... NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0 Total memory usage is 38140 kilobytes Writing NGD file "next_state_logic.ngd" ... Writing NGDBUILD log file "next_state_logic.bld"... NGDBUILD done. Completed process "Translate". Started process "Map". Using target part "3s200ft256-4". Removing unused or disabled logic... Running cover... Running directed packing... Running delay-based LUT packing... Running related packing... Design Summary: Number of errors: 0 Number of warnings: 0 Logic Utilization: Logic Distribution: Number of Slices containing only related logic: 0 out of 0 0% Number of Slices containing unrelated logic: 0 out of 0 0% *See NOTES below for an explanation of the effects of unrelated logic Number of bonded IOBs: 8 out of 173 4% IOB Flip Flops: 3 Number of GCLKs: 1 out of 8 12% Total equivalent gate count for design: 27 Additional JTAG gate count for IOBs: 384 Peak Memory Usage: 66 MB NOTES: Related logic is defined as being logic that shares connectivity - e.g. two LUTs are "related" if they share common inputs. When assembling slices, Map gives priority to combine logic that is related. Doing so results in the best timing performance. Unrelated logic shares no connectivity. Map will only begin packing unrelated logic into a slice once 99% of the slices are occupied through related logic packing. Note that once logic distribution reaches the 99% level through related logic packing, this does not mean the device is completely utilized. Unrelated logic packing will then begin, continuing until all usable LUTs and FFs are occupied. Depending on your timing budget, increased levels of unrelated logic packing may adversely affect the overall timing performance of your design. Mapping completed. See MAP report file "next_state_logic_map.mrp" for details. Completed process "Map". Mapping Module next_state_logic . . . MAP command line: map -intstyle ise -p xc3s200-ft256-4 -cm area -pr b -k 4 -c 100 -tx off -o next_state_logic_map.ncd next_state_logic.ngd next_state_logic.pcf Mapping Module next_state_logic: DONE Started process "Place & Route". Constraints file: next_state_logic.pcf Loading device database for application Par from file "next_state_logic_map.ncd". "next_state_logic" is an NCD, version 2.38, device xc3s200, package ft256, speed -4 Loading device for application Par from file '3s200.nph' in environment C:/Program Files/Xilinx. Device speed data version: PRODUCTION 1.32 2004-06-25. Resolving physical constraints. Finished resolving physical constraints. Device utilization summary: Number of External IOBs 8 out of 173 4% Number of LOCed External IOBs 0 out of 8 0% Number of BUFGMUXs 1 out of 8 12% Overall effort level (-ol): Standard (set by user) Placer effort level (-pl): Standard (set by user) Placer cost table entry (-t): 1 Router effort level (-rl): Standard (set by user) Phase 1.1 Phase 1.1 (Checksum:989691) REAL time: 0 secs . Phase 3.3 Phase 3.3 (Checksum:1c9c37d) REAL time: 0 secs Phase 4.5 Phase 4.5 (Checksum:26259fc) REAL time: 0 secs Phase 5.8 Phase 5.8 (Checksum:98b3cb) REAL time: 0 secs Phase 6.5 Phase 6.5 (Checksum:39386fa) REAL time: 0 secs Phase 7.18 Phase 7.18 (Checksum:42c1d79) REAL time: 0 secs Writing design to file next_state_logic.ncd. Total REAL time to Placer completion: 0 secs Total CPU time to Placer completion: 0 secs Phase 1: 11 unrouted; REAL time: 0 secs Phase 2: 7 unrouted; REAL time: 0 secs Phase 3: 0 unrouted; REAL time: 0 secs Phase 4: 0 unrouted; REAL time: 0 secs Total REAL time to Router completion: 0 secs Total CPU time to Router completion: 0 secs Generating "par" statistics. ************************** Generating Clock Report ************************** +-------------------------+----------+------+------+------------+-------------+ | Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)| +-------------------------+----------+------+------+------------+-------------+ | clk_BUFGP | BUFGMUX3| No | 3 | 0.001 | 1.051 | +-------------------------+----------+------+------+------------+-------------+ Generating Pad Report. All signals are completely routed. Total REAL time to PAR completion: 4 secs Total CPU time to PAR completion: 1 secs Peak Memory Usage: 55 MB Placement: Completed - No errors found. Routing: Completed - No errors found. Writing design to file next_state_logic.ncd. PAR done. Completed process "Place & Route". Started process "Generate Post-Place & Route Static Timing". Analysis completed Fri Mar 16 11:52:26 2007 -------------------------------------------------------------------------------- Generating Report ... Completed process "Generate Post-Place & Route Static Timing". Place & Route Module next_state_logic . . . PAR command line: par -w -intstyle ise -ol std -t 1 next_state_logic_map.ncd next_state_logic.ncd next_state_logic.pcf PAR completed successfully Started process "Generate Post-Place & Route Simulation Model". Completed process "Generate Post-Place & Route Simulation Model". Compiling vhdl file Z:/camurati/esercitazione_2/next_state_logic.vhd in Library work. Entity (Architecture ) compiled. Project Navigator Auto-Make Log File ------------------------------------- Started process "View VHDL Functional Model". Release 6.3i - sch2vhdl G.35 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. DRC Check completed: No Error found. Vhdl netlist file generated. Completed process "View VHDL Functional Model". Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file Z:/camurati/esercitazione_2/datapath.vhd in Library work. Architecture behavioral of Entity datapath is up to date. Compiling vhdl file Z:/camurati/esercitazione_2/next_state_logic.vhd in Library work. Architecture behavioral of Entity next_state_logic is up to date. Compiling vhdl file Z:/camurati/esercitazione_2/riconoscitore_1011.vhf in Library work. Entity (Architecture ) compiled. ========================================================================= * HDL Analysis * ========================================================================= Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is Z:/camurati/esercitazione_2/next_state_logic.vhd. Found 3-bit register for signal . Summary: inferred 3 D-type flip-flop(s). Unit synthesized. Synthesizing Unit . Related source file is Z:/camurati/esercitazione_2/datapath.vhd. Found 1-bit register for signal . Found 3-bit register for signal . Summary: inferred 4 D-type flip-flop(s). Unit synthesized. Synthesizing Unit . Related source file is Z:/camurati/esercitazione_2/riconoscitore_1011.vhf. Unit synthesized. ========================================================================= * Advanced HDL Synthesis * ========================================================================= Advanced RAM inference ... Advanced multiplier inference ... Advanced Registered AddSub inference ... Dynamic shift register inference ... ========================================================================= HDL Synthesis Report Macro Statistics # Registers : 3 1-bit register : 1 3-bit register : 2 ========================================================================= ========================================================================= * Low Level Synthesis * ========================================================================= Optimizing unit ... Optimizing unit ... Loading device for application Xst from file '3s200.nph' in environment C:/Program Files/Xilinx. Mapping all equations... Building and optimizing final netlist ... Found area constraint ratio of 100 (+ 5) on block riconoscitore_1011, actual ratio is 0. ========================================================================= * Final Report * ========================================================================= Device utilization summary: --------------------------- Selected Device : 3s200ft256-4 Number of Slices: 5 out of 1920 0% Number of Slice Flip Flops: 7 out of 3840 0% Number of 4 input LUTs: 7 out of 3840 0% Number of bonded IOBs: 7 out of 173 4% Number of GCLKs: 1 out of 8 12% ========================================================================= TIMING REPORT Clock Information: ------------------ -----------------------------------+------------------------+-------+ Clock Signal | Clock buffer(FF name) | Load | -----------------------------------+------------------------+-------+ Clock | BUFGP | 7 | -----------------------------------+------------------------+-------+ Timing Summary: --------------- Speed Grade: -4 Minimum period: 2.581ns (Maximum Frequency: 387.447MHz) Minimum input arrival time before clock: 3.732ns Maximum output required time after clock: 6.342ns Maximum combinational path delay: No path found ========================================================================= Completed process "Synthesize". Started process "Translate". Command Line: ngdbuild -intstyle ise -dd z:\camurati\esercitazione_2/_ngo -i -p xc3s200-ft256-4 riconoscitore_1011.ngc riconoscitore_1011.ngd Reading NGO file "Z:/camurati/esercitazione_2/riconoscitore_1011.ngc" ... Reading component libraries for design expansion... Checking timing specifications ... Checking expanded design ... NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0 Total memory usage is 38140 kilobytes Writing NGD file "riconoscitore_1011.ngd" ... Writing NGDBUILD log file "riconoscitore_1011.bld"... NGDBUILD done. Completed process "Translate". Started process "Map". Using target part "3s200ft256-4". Removing unused or disabled logic... Running cover... Running directed packing... Running delay-based LUT packing... Running related packing... Design Summary: Number of errors: 0 Number of warnings: 0 Logic Utilization: Number of Slice Flip Flops: 7 out of 3,840 1% Number of 4 input LUTs: 7 out of 3,840 1% Logic Distribution: Number of occupied Slices: 6 out of 1,920 1% Number of Slices containing only related logic: 6 out of 6 100% Number of Slices containing unrelated logic: 0 out of 6 0% *See NOTES below for an explanation of the effects of unrelated logic Total Number of 4 input LUTs: 7 out of 3,840 1% Number of bonded IOBs: 8 out of 173 4% Number of GCLKs: 1 out of 8 12% Total equivalent gate count for design: 110 Additional JTAG gate count for IOBs: 384 Peak Memory Usage: 66 MB NOTES: Related logic is defined as being logic that shares connectivity - e.g. two LUTs are "related" if they share common inputs. When assembling slices, Map gives priority to combine logic that is related. Doing so results in the best timing performance. Unrelated logic shares no connectivity. Map will only begin packing unrelated logic into a slice once 99% of the slices are occupied through related logic packing. Note that once logic distribution reaches the 99% level through related logic packing, this does not mean the device is completely utilized. Unrelated logic packing will then begin, continuing until all usable LUTs and FFs are occupied. Depending on your timing budget, increased levels of unrelated logic packing may adversely affect the overall timing performance of your design. Mapping completed. See MAP report file "riconoscitore_1011_map.mrp" for details. Completed process "Map". Mapping Module riconoscitore_1011 . . . MAP command line: map -intstyle ise -p xc3s200-ft256-4 -cm area -pr b -k 4 -c 100 -tx off -o riconoscitore_1011_map.ncd riconoscitore_1011.ngd riconoscitore_1011.pcf Mapping Module riconoscitore_1011: DONE Started process "Place & Route". Constraints file: riconoscitore_1011.pcf Loading device database for application Par from file "riconoscitore_1011_map.ncd". "riconoscitore_1011" is an NCD, version 2.38, device xc3s200, package ft256, speed -4 Loading device for application Par from file '3s200.nph' in environment C:/Program Files/Xilinx. Device speed data version: PRODUCTION 1.32 2004-06-25. Resolving physical constraints. Finished resolving physical constraints. Device utilization summary: Number of External IOBs 8 out of 173 4% Number of LOCed External IOBs 0 out of 8 0% Number of Slices 6 out of 1920 1% Number of BUFGMUXs 1 out of 8 12% Overall effort level (-ol): Standard (set by user) Placer effort level (-pl): Standard (set by user) Placer cost table entry (-t): 1 Router effort level (-rl): Standard (set by user) Phase 1.1 Phase 1.1 (Checksum:9896ac) REAL time: 0 secs Phase 3.3 Phase 3.3 (Checksum:1c9c37d) REAL time: 0 secs Phase 4.5 Phase 4.5 (Checksum:26259fc) REAL time: 0 secs Phase 5.8 . Phase 5.8 (Checksum:98a570) REAL time: 0 secs Phase 6.5 Phase 6.5 (Checksum:39386fa) REAL time: 0 secs Phase 7.18 Phase 7.18 (Checksum:42c1d79) REAL time: 0 secs Writing design to file riconoscitore_1011.ncd. Total REAL time to Placer completion: 0 secs Total CPU time to Placer completion: 0 secs Phase 1: 56 unrouted; REAL time: 0 secs Phase 2: 49 unrouted; REAL time: 0 secs Phase 3: 12 unrouted; REAL time: 0 secs Phase 4: 0 unrouted; REAL time: 0 secs Total REAL time to Router completion: 0 secs Total CPU time to Router completion: 0 secs Generating "par" statistics. ************************** Generating Clock Report ************************** +-------------------------+----------+------+------+------------+-------------+ | Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)| +-------------------------+----------+------+------+------------+-------------+ | Clock_BUFGP | BUFGMUX7| No | 6 | 0.000 | 1.011 | +-------------------------+----------+------+------+------------+-------------+ Generating Pad Report. All signals are completely routed. Total REAL time to PAR completion: 4 secs Total CPU time to PAR completion: 1 secs Peak Memory Usage: 56 MB Placement: Completed - No errors found. Routing: Completed - No errors found. Writing design to file riconoscitore_1011.ncd. PAR done. Completed process "Place & Route". Started process "Generate Post-Place & Route Static Timing". Analysis completed Fri Mar 16 11:53:32 2007 -------------------------------------------------------------------------------- Generating Report ... Completed process "Generate Post-Place & Route Static Timing". Place & Route Module riconoscitore_1011 . . . PAR command line: par -w -intstyle ise -ol std -t 1 riconoscitore_1011_map.ncd riconoscitore_1011.ncd riconoscitore_1011.pcf PAR completed successfully Started process "Generate Post-Place & Route Simulation Model". Completed process "Generate Post-Place & Route Simulation Model". Compiling vhdl file Z:/camurati/esercitazione_2/riconoscitore_1011.vhf in Library work. Entity (Architecture ) compiled. Project Navigator Auto-Make Log File ------------------------------------- Started process "Create Schematic Symbol". Compiling vhdl file Z:/camurati/esercitazione_2/datapath.vhd in Library work. Entity (Architecture ) compiled. tdtfi(vhdl) completed successfully. Release 6.3i - spl2sym G.35 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. Completed process "Create Schematic Symbol". Project Navigator Auto-Make Log File ------------------------------------- Started process "Create Schematic Symbol". Compiling vhdl file Z:/camurati/esercitazione_2/next_state_logic.vhd in Library work. Entity (Architecture ) compiled. tdtfi(vhdl) completed successfully. Release 6.3i - spl2sym G.35 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. Completed process "Create Schematic Symbol". Project Navigator Auto-Make Log File ------------------------------------- Started process "View VHDL Functional Model". Release 6.3i - sch2vhdl G.35 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. DRC Check completed: No Error found. Vhdl netlist file generated. Completed process "View VHDL Functional Model". Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file Z:/camurati/esercitazione_2/datapath.vhd in Library work. Architecture behavioral of Entity datapath is up to date. Compiling vhdl file Z:/camurati/esercitazione_2/next_state_logic.vhd in Library work. Architecture behavioral of Entity next_state_logic is up to date. Compiling vhdl file Z:/camurati/esercitazione_2/riconoscitore_1011.vhf in Library work. Entity (Architecture ) compiled. ========================================================================= * HDL Analysis * ========================================================================= Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is Z:/camurati/esercitazione_2/next_state_logic.vhd. Found 3-bit register for signal . Summary: inferred 3 D-type flip-flop(s). Unit synthesized. Synthesizing Unit . Related source file is Z:/camurati/esercitazione_2/datapath.vhd. Found 1-bit register for signal . Found 3-bit register for signal . Summary: inferred 4 D-type flip-flop(s). Unit synthesized. Synthesizing Unit . Related source file is Z:/camurati/esercitazione_2/riconoscitore_1011.vhf. Unit synthesized. ========================================================================= * Advanced HDL Synthesis * ========================================================================= Advanced RAM inference ... Advanced multiplier inference ... Advanced Registered AddSub inference ... Dynamic shift register inference ... ========================================================================= HDL Synthesis Report Macro Statistics # Registers : 3 1-bit register : 1 3-bit register : 2 ========================================================================= ========================================================================= * Low Level Synthesis * ========================================================================= Optimizing unit ... Optimizing unit ... Loading device for application Xst from file '3s200.nph' in environment C:/Program Files/Xilinx. Mapping all equations... Building and optimizing final netlist ... Found area constraint ratio of 100 (+ 5) on block riconoscitore_1011, actual ratio is 0. ========================================================================= * Final Report * ========================================================================= Device utilization summary: --------------------------- Selected Device : 3s200ft256-4 Number of Slices: 5 out of 1920 0% Number of Slice Flip Flops: 7 out of 3840 0% Number of 4 input LUTs: 7 out of 3840 0% Number of bonded IOBs: 7 out of 173 4% Number of GCLKs: 1 out of 8 12% ========================================================================= TIMING REPORT Clock Information: ------------------ -----------------------------------+------------------------+-------+ Clock Signal | Clock buffer(FF name) | Load | -----------------------------------+------------------------+-------+ Clock | BUFGP | 7 | -----------------------------------+------------------------+-------+ Timing Summary: --------------- Speed Grade: -4 Minimum period: 2.581ns (Maximum Frequency: 387.447MHz) Minimum input arrival time before clock: 3.732ns Maximum output required time after clock: 6.342ns Maximum combinational path delay: No path found ========================================================================= Completed process "Synthesize". Started process "Translate". Command Line: ngdbuild -intstyle ise -dd z:\camurati\esercitazione_2/_ngo -i -p xc3s200-ft256-4 riconoscitore_1011.ngc riconoscitore_1011.ngd Reading NGO file "Z:/camurati/esercitazione_2/riconoscitore_1011.ngc" ... Reading component libraries for design expansion... Checking timing specifications ... Checking expanded design ... NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0 Total memory usage is 38140 kilobytes Writing NGD file "riconoscitore_1011.ngd" ... Writing NGDBUILD log file "riconoscitore_1011.bld"... NGDBUILD done. Completed process "Translate". Started process "Map". Using target part "3s200ft256-4". Removing unused or disabled logic... Running cover... Running directed packing... Running delay-based LUT packing... Running related packing... Design Summary: Number of errors: 0 Number of warnings: 0 Logic Utilization: Number of Slice Flip Flops: 7 out of 3,840 1% Number of 4 input LUTs: 7 out of 3,840 1% Logic Distribution: Number of occupied Slices: 6 out of 1,920 1% Number of Slices containing only related logic: 6 out of 6 100% Number of Slices containing unrelated logic: 0 out of 6 0% *See NOTES below for an explanation of the effects of unrelated logic Total Number of 4 input LUTs: 7 out of 3,840 1% Number of bonded IOBs: 8 out of 173 4% Number of GCLKs: 1 out of 8 12% Total equivalent gate count for design: 110 Additional JTAG gate count for IOBs: 384 Peak Memory Usage: 66 MB NOTES: Related logic is defined as being logic that shares connectivity - e.g. two LUTs are "related" if they share common inputs. When assembling slices, Map gives priority to combine logic that is related. Doing so results in the best timing performance. Unrelated logic shares no connectivity. Map will only begin packing unrelated logic into a slice once 99% of the slices are occupied through related logic packing. Note that once logic distribution reaches the 99% level through related logic packing, this does not mean the device is completely utilized. Unrelated logic packing will then begin, continuing until all usable LUTs and FFs are occupied. Depending on your timing budget, increased levels of unrelated logic packing may adversely affect the overall timing performance of your design. Mapping completed. See MAP report file "riconoscitore_1011_map.mrp" for details. Completed process "Map". Mapping Module riconoscitore_1011 . . . MAP command line: map -intstyle ise -p xc3s200-ft256-4 -cm area -pr b -k 4 -c 100 -tx off -o riconoscitore_1011_map.ncd riconoscitore_1011.ngd riconoscitore_1011.pcf Mapping Module riconoscitore_1011: DONE Started process "Place & Route". Constraints file: riconoscitore_1011.pcf Loading device database for application Par from file "riconoscitore_1011_map.ncd". "riconoscitore_1011" is an NCD, version 2.38, device xc3s200, package ft256, speed -4 Loading device for application Par from file '3s200.nph' in environment C:/Program Files/Xilinx. Device speed data version: PRODUCTION 1.32 2004-06-25. Resolving physical constraints. Finished resolving physical constraints. Device utilization summary: Number of External IOBs 8 out of 173 4% Number of LOCed External IOBs 0 out of 8 0% Number of Slices 6 out of 1920 1% Number of BUFGMUXs 1 out of 8 12% Overall effort level (-ol): Standard (set by user) Placer effort level (-pl): Standard (set by user) Placer cost table entry (-t): 1 Router effort level (-rl): Standard (set by user) Phase 1.1 Phase 1.1 (Checksum:9896ac) REAL time: 0 secs Phase 3.3 Phase 3.3 (Checksum:1c9c37d) REAL time: 0 secs Phase 4.5 Phase 4.5 (Checksum:26259fc) REAL time: 0 secs Phase 5.8 . Phase 5.8 (Checksum:98a570) REAL time: 0 secs Phase 6.5 Phase 6.5 (Checksum:39386fa) REAL time: 0 secs Phase 7.18 Phase 7.18 (Checksum:42c1d79) REAL time: 0 secs Writing design to file riconoscitore_1011.ncd. Total REAL time to Placer completion: 0 secs Total CPU time to Placer completion: 0 secs Phase 1: 56 unrouted; REAL time: 0 secs Phase 2: 49 unrouted; REAL time: 0 secs Phase 3: 12 unrouted; REAL time: 0 secs Phase 4: 0 unrouted; REAL time: 0 secs Total REAL time to Router completion: 0 secs Total CPU time to Router completion: 0 secs Generating "par" statistics. ************************** Generating Clock Report ************************** +-------------------------+----------+------+------+------------+-------------+ | Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)| +-------------------------+----------+------+------+------------+-------------+ | Clock_BUFGP | BUFGMUX7| No | 6 | 0.000 | 1.011 | +-------------------------+----------+------+------+------------+-------------+ Generating Pad Report. All signals are completely routed. Total REAL time to PAR completion: 4 secs Total CPU time to PAR completion: 1 secs Peak Memory Usage: 56 MB Placement: Completed - No errors found. Routing: Completed - No errors found. Writing design to file riconoscitore_1011.ncd. PAR done. Completed process "Place & Route". Started process "Generate Post-Place & Route Static Timing". Analysis completed Fri Mar 16 11:55:26 2007 -------------------------------------------------------------------------------- Generating Report ... Completed process "Generate Post-Place & Route Static Timing". Place & Route Module riconoscitore_1011 . . . PAR command line: par -w -intstyle ise -ol std -t 1 riconoscitore_1011_map.ncd riconoscitore_1011.ncd riconoscitore_1011.pcf PAR completed successfully Started process "Generate Post-Place & Route Simulation Model". Completed process "Generate Post-Place & Route Simulation Model". Compiling vhdl file Z:/camurati/esercitazione_2/riconoscitore_1011.vhf in Library work. Entity (Architecture ) compiled. Project Navigator Auto-Make Log File ------------------------------------- Started process "Create Schematic Symbol". Compiling vhdl file Z:/camurati/esercitazione_2/datapath.vhd in Library work. Entity (Architecture ) compiled. tdtfi(vhdl) completed successfully. Release 6.3i - spl2sym G.35 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. Completed process "Create Schematic Symbol". Project Navigator Auto-Make Log File ------------------------------------- Started process "Check Syntax". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file Z:/camurati/esercitazione_2/datapath.vhd in Library work. Architecture behavioral of Entity datapath is up to date. Completed process "Check Syntax". Project Navigator Auto-Make Log File ------------------------------------- Started process "View VHDL Functional Model". Release 6.3i - sch2vhdl G.35 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. DRC Check completed: No Error found. Vhdl netlist file generated. Completed process "View VHDL Functional Model". Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file Z:/camurati/esercitazione_2/datapath.vhd in Library work. Architecture behavioral of Entity datapath is up to date. Compiling vhdl file Z:/camurati/esercitazione_2/next_state_logic.vhd in Library work. Architecture behavioral of Entity next_state_logic is up to date. Compiling vhdl file Z:/camurati/esercitazione_2/riconoscitore_1011.vhf in Library work. Entity (Architecture ) compiled. ========================================================================= * HDL Analysis * ========================================================================= Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). WARNING:Xst:819 - Z:/camurati/esercitazione_2/datapath.vhd line 21: The following signals are missing in the process sensitivity list: en, x. Entity analyzed. Unit generated. Analyzing Entity (Architecture ). Entity analyzed. Unit generated. ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is Z:/camurati/esercitazione_2/next_state_logic.vhd. Found 3-bit register for signal . Summary: inferred 3 D-type flip-flop(s). Unit synthesized. Synthesizing Unit . Related source file is Z:/camurati/esercitazione_2/datapath.vhd. WARNING:Xst:647 - Input is never used. WARNING:Xst:647 - Input is never used. WARNING:Xst:737 - Found 1-bit latch for signal . WARNING:Xst:736 - Found 3-bit latch for signal <$n0007> created at line 30. Unit synthesized. Synthesizing Unit . Related source file is Z:/camurati/esercitazione_2/riconoscitore_1011.vhf. Unit synthesized. ========================================================================= * Advanced HDL Synthesis * ========================================================================= Advanced RAM inference ... Advanced multiplier inference ... Advanced Registered AddSub inference ... Dynamic shift register inference ... ========================================================================= HDL Synthesis Report Macro Statistics # Registers : 1 3-bit register : 1 # Latches : 2 1-bit latch : 1 3-bit latch : 1 ========================================================================= ========================================================================= * Low Level Synthesis * ========================================================================= Optimizing unit ... Optimizing unit ... Loading device for application Xst from file '3s200.nph' in environment C:/Program Files/Xilinx. Mapping all equations... Building and optimizing final netlist ... Found area constraint ratio of 100 (+ 5) on block riconoscitore_1011, actual ratio is 0. FlipFlop XLXI_4_nstate_2 has been replicated 1 time(s) to handle iob=true attribute. FlipFlop XLXI_4_nstate_1 has been replicated 1 time(s) to handle iob=true attribute. FlipFlop XLXI_4_nstate_0 has been replicated 1 time(s) to handle iob=true attribute. ========================================================================= * Final Report * ========================================================================= Device utilization summary: --------------------------- Selected Device : 3s200ft256-4 Number of Slices: 8 out of 1920 0% Number of Slice Flip Flops: 10 out of 3840 0% Number of 4 input LUTs: 9 out of 3840 0% Number of bonded IOBs: 6 out of 173 3% Number of GCLKs: 2 out of 8 25% ========================================================================= TIMING REPORT Clock Information: ------------------ -----------------------------------+------------------------+-------+ Clock Signal | Clock buffer(FF name) | Load | -----------------------------------+------------------------+-------+ Clock | BUFGP | 6 | Enable | BUFGP | 4 | -----------------------------------+------------------------+-------+ Timing Summary: --------------- Speed Grade: -4 Minimum period: 1.964ns (Maximum Frequency: 509.165MHz) Minimum input arrival time before clock: 4.133ns Maximum output required time after clock: 5.973ns Maximum combinational path delay: No path found ========================================================================= Completed process "Synthesize". Started process "Translate". Command Line: ngdbuild -intstyle ise -dd z:\camurati\esercitazione_2/_ngo -i -p xc3s200-ft256-4 riconoscitore_1011.ngc riconoscitore_1011.ngd Reading NGO file "Z:/camurati/esercitazione_2/riconoscitore_1011.ngc" ... Reading component libraries for design expansion... Checking timing specifications ... Checking expanded design ... NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0 Total memory usage is 38140 kilobytes Writing NGD file "riconoscitore_1011.ngd" ... Writing NGDBUILD log file "riconoscitore_1011.bld"... NGDBUILD done. Completed process "Translate". Started process "Map". Using target part "3s200ft256-4". Removing unused or disabled logic... Running cover... Running directed packing... Running delay-based LUT packing... Running related packing... Design Summary: Number of errors: 0 Number of warnings: 0 Logic Utilization: Total Number Slice Registers: 7 out of 3,840 1% Number used as Flip Flops: 3 Number used as Latches: 4 Number of 4 input LUTs: 9 out of 3,840 1% Logic Distribution: Number of occupied Slices: 7 out of 1,920 1% Number of Slices containing only related logic: 7 out of 7 100% Number of Slices containing unrelated logic: 0 out of 7 0% *See NOTES below for an explanation of the effects of unrelated logic Total Number of 4 input LUTs: 9 out of 3,840 1% Number of bonded IOBs: 8 out of 173 4% IOB Flip Flops: 3 Number of GCLKs: 2 out of 8 25% Total equivalent gate count for design: 128 Additional JTAG gate count for IOBs: 384 Peak Memory Usage: 66 MB NOTES: Related logic is defined as being logic that shares connectivity - e.g. two LUTs are "related" if they share common inputs. When assembling slices, Map gives priority to combine logic that is related. Doing so results in the best timing performance. Unrelated logic shares no connectivity. Map will only begin packing unrelated logic into a slice once 99% of the slices are occupied through related logic packing. Note that once logic distribution reaches the 99% level through related logic packing, this does not mean the device is completely utilized. Unrelated logic packing will then begin, continuing until all usable LUTs and FFs are occupied. Depending on your timing budget, increased levels of unrelated logic packing may adversely affect the overall timing performance of your design. Mapping completed. See MAP report file "riconoscitore_1011_map.mrp" for details. Completed process "Map". Mapping Module riconoscitore_1011 . . . MAP command line: map -intstyle ise -p xc3s200-ft256-4 -cm area -pr b -k 4 -c 100 -tx off -o riconoscitore_1011_map.ncd riconoscitore_1011.ngd riconoscitore_1011.pcf Mapping Module riconoscitore_1011: DONE Started process "Place & Route". Constraints file: riconoscitore_1011.pcf Loading device database for application Par from file "riconoscitore_1011_map.ncd". "riconoscitore_1011" is an NCD, version 2.38, device xc3s200, package ft256, speed -4 Loading device for application Par from file '3s200.nph' in environment C:/Program Files/Xilinx. Device speed data version: PRODUCTION 1.32 2004-06-25. Resolving physical constraints. Finished resolving physical constraints. Device utilization summary: Number of External IOBs 8 out of 173 4% Number of LOCed External IOBs 0 out of 8 0% Number of Slices 7 out of 1920 1% Number of BUFGMUXs 2 out of 8 25% Overall effort level (-ol): Standard (set by user) Placer effort level (-pl): Standard (set by user) Placer cost table entry (-t): 1 Router effort level (-rl): Standard (set by user) Phase 1.1 Phase 1.1 (Checksum:9896b2) REAL time: 0 secs . Phase 3.3 Phase 3.3 (Checksum:1c9c37d) REAL time: 0 secs Phase 4.5 Phase 4.5 (Checksum:26259fc) REAL time: 0 secs Phase 5.8 . Phase 5.8 (Checksum:98e0e9) REAL time: 0 secs Phase 6.5 Phase 6.5 (Checksum:39386fa) REAL time: 0 secs Phase 7.18 Phase 7.18 (Checksum:42c1d79) REAL time: 0 secs Writing design to file riconoscitore_1011.ncd. Total REAL time to Placer completion: 0 secs Total CPU time to Placer completion: 0 secs Phase 1: 59 unrouted; REAL time: 0 secs Phase 2: 48 unrouted; REAL time: 0 secs Phase 3: 13 unrouted; REAL time: 0 secs Phase 4: 0 unrouted; REAL time: 0 secs Total REAL time to Router completion: 0 secs Total CPU time to Router completion: 0 secs Generating "par" statistics. ************************** Generating Clock Report ************************** +-------------------------+----------+------+------+------------+-------------+ | Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)| +-------------------------+----------+------+------+------------+-------------+ | Clock_BUFGP | BUFGMUX7| No | 5 | 0.041 | 1.051 | +-------------------------+----------+------+------+------------+-------------+ | Enable_BUFGP | BUFGMUX2| No | 4 | 0.000 | 1.010 | +-------------------------+----------+------+------+------------+-------------+ Generating Pad Report. All signals are completely routed. Total REAL time to PAR completion: 4 secs Total CPU time to PAR completion: 1 secs Peak Memory Usage: 56 MB Placement: Completed - No errors found. Routing: Completed - No errors found. Writing design to file riconoscitore_1011.ncd. PAR done. Completed process "Place & Route". Started process "Generate Post-Place & Route Static Timing". Analysis completed Fri Mar 16 11:59:49 2007 -------------------------------------------------------------------------------- Generating Report ... Completed process "Generate Post-Place & Route Static Timing". Place & Route Module riconoscitore_1011 . . . PAR command line: par -w -intstyle ise -ol std -t 1 riconoscitore_1011_map.ncd riconoscitore_1011.ncd riconoscitore_1011.pcf PAR completed successfully Started process "Generate Post-Place & Route Simulation Model". Completed process "Generate Post-Place & Route Simulation Model". Compiling vhdl file Z:/camurati/esercitazione_2/riconoscitore_1011.vhf in Library work. Entity (Architecture ) compiled.