-- Z:\CAMURATI\ESERCITAZIONE_1 -- VHDL Test Bench created by -- HDL Bencher 6.1i -- Fri Mar 02 09:35:03 2007 -- -- Notes: -- 1) This testbench has been automatically generated from -- your Test Bench Waveform -- 2) To use this as a user modifiable testbench do the following: -- - Save it as a file with a .vhd extension (i.e. File->Save As...) -- - Add it to your project as a testbench source (i.e. Project->Add Source...) -- LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; USE IEEE.STD_LOGIC_TEXTIO.ALL; USE STD.TEXTIO.ALL; ENTITY test_fa IS END test_fa; ARCHITECTURE testbench_arch OF test_fa IS -- If you get a compiler error on the following line, -- from the menu do Options->Configuration select VHDL 87 FILE RESULTS: TEXT OPEN WRITE_MODE IS "results.txt"; COMPONENT es_1 PORT ( A : In std_logic; B : In std_logic; C_in : In std_logic; ce : In std_logic; S0 : Out std_logic; C_out : Out std_logic ); END COMPONENT; SIGNAL A : std_logic; SIGNAL B : std_logic; SIGNAL C_in : std_logic; SIGNAL ce : std_logic; SIGNAL S0 : std_logic; SIGNAL C_out : std_logic; BEGIN UUT : es_1 PORT MAP ( A => A, B => B, C_in => C_in, ce => ce, S0 => S0, C_out => C_out ); PROCESS VARIABLE TX_OUT : LINE; VARIABLE TX_ERROR : INTEGER := 0; PROCEDURE CHECK_S0( next_S0 : std_logic; TX_TIME : INTEGER ) IS VARIABLE TX_STR : String(1 to 4096); VARIABLE TX_LOC : LINE; BEGIN -- If compiler error ("/=" is ambiguous) occurs in the next line of code -- change compiler settings to use explicit declarations only IF (S0 /= next_S0) THEN STD.TEXTIO.write(TX_LOC,string'("Error at time=")); STD.TEXTIO.write(TX_LOC, TX_TIME); STD.TEXTIO.write(TX_LOC,string'("ns S0=")); IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, S0); STD.TEXTIO.write(TX_LOC, string'(", Expected = ")); IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, next_S0); STD.TEXTIO.write(TX_LOC, string'(" ")); TX_STR(TX_LOC.all'range) := TX_LOC.all; STD.TEXTIO.writeline(results, TX_LOC); STD.TEXTIO.Deallocate(TX_LOC); ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR; TX_ERROR := TX_ERROR + 1; END IF; END; PROCEDURE CHECK_C_out( next_C_out : std_logic; TX_TIME : INTEGER ) IS VARIABLE TX_STR : String(1 to 4096); VARIABLE TX_LOC : LINE; BEGIN -- If compiler error ("/=" is ambiguous) occurs in the next line of code -- change compiler settings to use explicit declarations only IF (C_out /= next_C_out) THEN STD.TEXTIO.write(TX_LOC,string'("Error at time=")); STD.TEXTIO.write(TX_LOC, TX_TIME); STD.TEXTIO.write(TX_LOC,string'("ns C_out=")); IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, C_out); STD.TEXTIO.write(TX_LOC, string'(", Expected = ")); IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, next_C_out); STD.TEXTIO.write(TX_LOC, string'(" ")); TX_STR(TX_LOC.all'range) := TX_LOC.all; STD.TEXTIO.writeline(results, TX_LOC); STD.TEXTIO.Deallocate(TX_LOC); ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR; TX_ERROR := TX_ERROR + 1; END IF; END; BEGIN -- -------------------- A <= transport '0'; B <= transport '0'; C_in <= transport '0'; ce <= transport '0'; -- -------------------- WAIT FOR 50 ns; -- Time=50 ns CHECK_S0('0',50); CHECK_C_out('0',50); -- -------------------- WAIT FOR 100 ns; -- Time=150 ns CHECK_S0('0',150); CHECK_C_out('0',150); -- -------------------- WAIT FOR 100 ns; -- Time=250 ns CHECK_S0('0',250); CHECK_C_out('0',250); -- -------------------- WAIT FOR 100 ns; -- Time=350 ns CHECK_S0('0',350); CHECK_C_out('0',350); -- -------------------- WAIT FOR 100 ns; -- Time=450 ns CHECK_S0('0',450); CHECK_C_out('0',450); -- -------------------- WAIT FOR 100 ns; -- Time=550 ns CHECK_S0('0',550); CHECK_C_out('0',550); -- -------------------- WAIT FOR 100 ns; -- Time=650 ns CHECK_S0('0',650); CHECK_C_out('0',650); -- -------------------- WAIT FOR 100 ns; -- Time=750 ns CHECK_S0('0',750); CHECK_C_out('0',750); -- -------------------- WAIT FOR 100 ns; -- Time=850 ns CHECK_S0('0',850); CHECK_C_out('0',850); -- -------------------- WAIT FOR 100 ns; -- Time=950 ns CHECK_S0('0',950); CHECK_C_out('0',950); -- -------------------- WAIT FOR 50 ns; -- Time=1000 ns A <= transport '1'; B <= transport '1'; C_in <= transport '1'; ce <= transport '1'; -- -------------------- WAIT FOR 50 ns; -- Time=1050 ns CHECK_S0('1',1050); CHECK_C_out('1',1050); -- -------------------- WAIT FOR 100 ns; -- Time=1150 ns CHECK_S0('1',1150); CHECK_C_out('1',1150); -- -------------------- WAIT FOR 50 ns; -- Time=1200 ns C_in <= transport '0'; -- -------------------- WAIT FOR 50 ns; -- Time=1250 ns CHECK_S0('0',1250); CHECK_C_out('1',1250); -- -------------------- WAIT FOR 100 ns; -- Time=1350 ns CHECK_S0('0',1350); CHECK_C_out('1',1350); -- -------------------- WAIT FOR 50 ns; -- Time=1400 ns B <= transport '0'; -- -------------------- WAIT FOR 50 ns; -- Time=1450 ns CHECK_S0('1',1450); CHECK_C_out('0',1450); -- -------------------- WAIT FOR 100 ns; -- Time=1550 ns CHECK_S0('1',1550); CHECK_C_out('0',1550); -- -------------------- WAIT FOR 50 ns; -- Time=1600 ns A <= transport '0'; -- -------------------- WAIT FOR 50 ns; -- Time=1650 ns CHECK_S0('0',1650); CHECK_C_out('0',1650); -- -------------------- WAIT FOR 100 ns; -- Time=1750 ns CHECK_S0('0',1750); CHECK_C_out('0',1750); -- -------------------- WAIT FOR 50 ns; -- Time=1800 ns C_in <= transport '1'; -- -------------------- WAIT FOR 50 ns; -- Time=1850 ns CHECK_S0('1',1850); CHECK_C_out('0',1850); -- -------------------- WAIT FOR 100 ns; -- Time=1950 ns -- -------------------- IF (TX_ERROR = 0) THEN STD.TEXTIO.write(TX_OUT,string'("No errors or warnings")); STD.TEXTIO.writeline(results, TX_OUT); ASSERT (FALSE) REPORT "Simulation successful (not a failure). No problems detected. " SEVERITY FAILURE; ELSE STD.TEXTIO.write(TX_OUT, TX_ERROR); STD.TEXTIO.write(TX_OUT, string'( " errors found in simulation")); STD.TEXTIO.writeline(results, TX_OUT); ASSERT (FALSE) REPORT "Errors found during simulation" SEVERITY FAILURE; END IF; END PROCESS; END testbench_arch; CONFIGURATION es_1_cfg OF test_fa IS FOR testbench_arch END FOR; END es_1_cfg;