## NOTE: Do not edit this file.
## Auto generated by Project Navigator for VHDL Post-PAR Simulation
##
vlib work
## Compile Post-PAR Model for Module es_1
vcom -87 -explicit  es_1_timesim.vhd
vcom -93 -explicit  test_fa.timesim_vhw
vsim -t 1ps -sdfmax /UUT=es_1_timesim.sdf  -lib work test_fa
do test_fa.udo
view wave
add wave *
view structure
view signals
run -all
## End