-- Xilinx Vhdl netlist produced by netgen application (version G.35)
-- Command       : -intstyle ise -s 4 -pcf ripple_carry_adder.pcf -ngm ripple_carry_adder.ngm -rpw 100 -tpw 0 -ar Structure -xon true -w -ofmt vhdl -sim ripple_carry_adder.ncd ripple_carry_adder_timesim.vhd 
-- Input file    : ripple_carry_adder.ncd
-- Output file   : ripple_carry_adder_timesim.vhd
-- Design name   : ripple_carry_adder
-- # of Entities : 1
-- Xilinx        : C:/Program Files/Xilinx
-- Device        : 3s200ft256-4 (PRODUCTION 1.32 2004-06-25)

-- This vhdl netlist is a simulation model and uses simulation 
-- primitives which may not represent the true implementation of the 
-- device, however the netlist is functionally correct and should not 
-- be modified. This file cannot be synthesized and should only be used 
-- with supported simulation tools.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library SIMPRIM;
use SIMPRIM.VCOMPONENTS.ALL;
use SIMPRIM.VPACKAGE.ALL;

entity ripple_carry_adder is
  port (
    Carry_out : out STD_LOGIC; 
    Carry_in : in STD_LOGIC := 'X'; 
    Enable : in STD_LOGIC := 'X'; 
    S : out STD_LOGIC_VECTOR ( 3 downto 0 ); 
    B : in STD_LOGIC_VECTOR ( 3 downto 0 ); 
    A : in STD_LOGIC_VECTOR ( 3 downto 0 ) 
  );
end ripple_carry_adder;

architecture Structure of ripple_carry_adder is
  signal Carry_in_IBUF : STD_LOGIC; 
  signal A_0_IBUF : STD_LOGIC; 
  signal A_1_IBUF : STD_LOGIC; 
  signal A_2_IBUF : STD_LOGIC; 
  signal A_3_IBUF : STD_LOGIC; 
  signal B_0_IBUF : STD_LOGIC; 
  signal B_1_IBUF : STD_LOGIC; 
  signal B_2_IBUF : STD_LOGIC; 
  signal B_3_IBUF : STD_LOGIC; 
  signal S_0_OBUF : STD_LOGIC; 
  signal S_1_OBUF : STD_LOGIC; 
  signal S_2_OBUF : STD_LOGIC; 
  signal S_3_OBUF : STD_LOGIC; 
  signal Carry_out_OBUF : STD_LOGIC; 
  signal Enable_IBUF : STD_LOGIC; 
  signal SF336 : STD_LOGIC; 
  signal N1281 : STD_LOGIC; 
  signal SF332 : STD_LOGIC; 
  signal SF338 : STD_LOGIC; 
  signal N1175 : STD_LOGIC; 
  signal N1368 : STD_LOGIC; 
  signal GSR : STD_LOGIC; 
  signal GTS : STD_LOGIC; 
  signal Carry_in_INBUF : STD_LOGIC; 
  signal A_0_INBUF : STD_LOGIC; 
  signal A_1_INBUF : STD_LOGIC; 
  signal A_2_INBUF : STD_LOGIC; 
  signal A_3_INBUF : STD_LOGIC; 
  signal B_0_INBUF : STD_LOGIC; 
  signal B_1_INBUF : STD_LOGIC; 
  signal B_2_INBUF : STD_LOGIC; 
  signal B_3_INBUF : STD_LOGIC; 
  signal S_0_ENABLE : STD_LOGIC; 
  signal S_0_GTS_OR_T : STD_LOGIC; 
  signal S_0_O : STD_LOGIC; 
  signal S_1_ENABLE : STD_LOGIC; 
  signal S_1_GTS_OR_T : STD_LOGIC; 
  signal S_1_O : STD_LOGIC; 
  signal S_2_ENABLE : STD_LOGIC; 
  signal S_2_GTS_OR_T : STD_LOGIC; 
  signal S_2_O : STD_LOGIC; 
  signal S_3_ENABLE : STD_LOGIC; 
  signal S_3_GTS_OR_T : STD_LOGIC; 
  signal S_3_O : STD_LOGIC; 
  signal Carry_out_ENABLE : STD_LOGIC; 
  signal Carry_out_GTS_OR_T : STD_LOGIC; 
  signal Carry_out_O : STD_LOGIC; 
  signal Enable_INBUF : STD_LOGIC; 
  signal S_0_OBUF_F : STD_LOGIC; 
  signal S_0_OBUF_G : STD_LOGIC; 
  signal S_2_OBUF_F : STD_LOGIC; 
  signal S_2_OBUF_G : STD_LOGIC; 
  signal S_3_OBUF_F : STD_LOGIC; 
  signal S_3_OBUF_G : STD_LOGIC; 
  signal Carry_out_OBUF_G : STD_LOGIC; 
  signal S_1_OBUF_F : STD_LOGIC; 
  signal S_1_OBUF_G : STD_LOGIC; 
  signal N1175_F : STD_LOGIC; 
  signal N1175_G : STD_LOGIC; 
  signal VCC : STD_LOGIC; 
begin
  Carry_in_IBUF_0 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => Carry_in,
      O => Carry_in_INBUF
    );
  A_0_IBUF_1 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => A(0),
      O => A_0_INBUF
    );
  A_1_IBUF_2 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => A(1),
      O => A_1_INBUF
    );
  A_2_IBUF_3 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => A(2),
      O => A_2_INBUF
    );
  A_3_IBUF_4 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => A(3),
      O => A_3_INBUF
    );
  B_0_IBUF_5 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => B(0),
      O => B_0_INBUF
    );
  B_1_IBUF_6 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => B(1),
      O => B_1_INBUF
    );
  B_2_IBUF_7 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => B(2),
      O => B_2_INBUF
    );
  B_3_IBUF_8 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => B(3),
      O => B_3_INBUF
    );
  S_0_OBUF_9 : X_TRI_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => S_0_O,
      CTL => S_0_ENABLE,
      O => S(0)
    );
  S_0_ENABLEINV : X_INV
    port map (
      I => S_0_GTS_OR_T,
      O => S_0_ENABLE
    );
  S_0_GTS_OR_T_10 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => GTS,
      O => S_0_GTS_OR_T
    );
  S_1_OBUF_11 : X_TRI_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => S_1_O,
      CTL => S_1_ENABLE,
      O => S(1)
    );
  S_1_ENABLEINV : X_INV
    port map (
      I => S_1_GTS_OR_T,
      O => S_1_ENABLE
    );
  S_1_GTS_OR_T_12 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => GTS,
      O => S_1_GTS_OR_T
    );
  S_2_OBUF_13 : X_TRI_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => S_2_O,
      CTL => S_2_ENABLE,
      O => S(2)
    );
  S_2_ENABLEINV : X_INV
    port map (
      I => S_2_GTS_OR_T,
      O => S_2_ENABLE
    );
  S_2_GTS_OR_T_14 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => GTS,
      O => S_2_GTS_OR_T
    );
  S_3_OBUF_15 : X_TRI_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => S_3_O,
      CTL => S_3_ENABLE,
      O => S(3)
    );
  S_3_ENABLEINV : X_INV
    port map (
      I => S_3_GTS_OR_T,
      O => S_3_ENABLE
    );
  S_3_GTS_OR_T_16 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => GTS,
      O => S_3_GTS_OR_T
    );
  Carry_out_OBUF_17 : X_TRI_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => Carry_out_O,
      CTL => Carry_out_ENABLE,
      O => Carry_out
    );
  Carry_out_ENABLEINV : X_INV
    port map (
      I => Carry_out_GTS_OR_T,
      O => Carry_out_ENABLE
    );
  Carry_out_GTS_OR_T_18 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => GTS,
      O => Carry_out_GTS_OR_T
    );
  Enable_IBUF_19 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => Enable,
      O => Enable_INBUF
    );
  S_0_OBUF_XUSED : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => S_0_OBUF_F,
      O => S_0_OBUF
    );
  S_0_OBUF_YUSED : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => S_0_OBUF_G,
      O => SF336
    );
  S_2_OBUF_XUSED : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => S_2_OBUF_F,
      O => S_2_OBUF
    );
  S_2_OBUF_YUSED : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => S_2_OBUF_G,
      O => N1281
    );
  SF338_20 : X_LUT4
    generic map(
      INIT => X"EE88"
    )
    port map (
      ADR0 => N1175,
      ADR1 => B_2_IBUF,
      ADR2 => VCC,
      ADR3 => A_2_IBUF,
      O => S_3_OBUF_G
    );
  S_3_OBUF_XUSED : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => S_3_OBUF_F,
      O => S_3_OBUF
    );
  S_3_OBUF_YUSED : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => S_3_OBUF_G,
      O => SF338
    );
  Carry_out_OBUF_YUSED : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => Carry_out_OBUF_G,
      O => Carry_out_OBUF
    );
  S_1_OBUF_XUSED : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => S_1_OBUF_F,
      O => S_1_OBUF
    );
  S_1_OBUF_YUSED : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => S_1_OBUF_G,
      O => N1368
    );
  N1175_XUSED : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => N1175_F,
      O => N1175
    );
  N1175_YUSED : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => N1175_G,
      O => SF332
    );
  SF3361 : X_LUT4
    generic map(
      INIT => X"EA80"
    )
    port map (
      ADR0 => A_1_IBUF,
      ADR1 => B_0_IBUF,
      ADR2 => A_0_IBUF,
      ADR3 => B_1_IBUF,
      O => S_0_OBUF_G
    );
  XLXI_4_sum1 : X_LUT4
    generic map(
      INIT => X"9060"
    )
    port map (
      ADR0 => A_0_IBUF,
      ADR1 => B_0_IBUF,
      ADR2 => Enable_IBUF,
      ADR3 => Carry_in_IBUF,
      O => S_0_OBUF_F
    );
  XLXI_2_sum_SW0 : X_LUT4
    generic map(
      INIT => X"03F3"
    )
    port map (
      ADR0 => VCC,
      ADR1 => SF336,
      ADR2 => Carry_in_IBUF,
      ADR3 => SF332,
      O => S_2_OBUF_G
    );
  XLXI_2_sum : X_LUT4
    generic map(
      INIT => X"6090"
    )
    port map (
      ADR0 => A_2_IBUF,
      ADR1 => B_2_IBUF,
      ADR2 => Enable_IBUF,
      ADR3 => N1281,
      O => S_2_OBUF_F
    );
  XLXI_1_carry_out1 : X_LUT4
    generic map(
      INIT => X"E080"
    )
    port map (
      ADR0 => SF338,
      ADR1 => A_3_IBUF,
      ADR2 => Enable_IBUF,
      ADR3 => B_3_IBUF,
      O => Carry_out_OBUF_G
    );
  XLXI_1_sum1 : X_LUT4
    generic map(
      INIT => X"9060"
    )
    port map (
      ADR0 => SF338,
      ADR1 => A_3_IBUF,
      ADR2 => Enable_IBUF,
      ADR3 => B_3_IBUF,
      O => S_3_OBUF_F
    );
  XLXI_3_sum_SW0 : X_LUT4
    generic map(
      INIT => X"033F"
    )
    port map (
      ADR0 => VCC,
      ADR1 => Carry_in_IBUF,
      ADR2 => B_0_IBUF,
      ADR3 => A_0_IBUF,
      O => S_1_OBUF_G
    );
  SF3321 : X_LUT4
    generic map(
      INIT => X"FEA8"
    )
    port map (
      ADR0 => B_1_IBUF,
      ADR1 => A_0_IBUF,
      ADR2 => B_0_IBUF,
      ADR3 => A_1_IBUF,
      O => N1175_G
    );
  XLXI_3_sum : X_LUT4
    generic map(
      INIT => X"4884"
    )
    port map (
      ADR0 => B_1_IBUF,
      ADR1 => Enable_IBUF,
      ADR2 => N1368,
      ADR3 => A_1_IBUF,
      O => S_1_OBUF_F
    );
  SF338_SW0 : X_LUT4
    generic map(
      INIT => X"FC0C"
    )
    port map (
      ADR0 => VCC,
      ADR1 => SF336,
      ADR2 => Carry_in_IBUF,
      ADR3 => SF332,
      O => N1175_F
    );
  Carry_in_IFF_IMUX : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => Carry_in_INBUF,
      O => Carry_in_IBUF
    );
  A_0_IFF_IMUX : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => A_0_INBUF,
      O => A_0_IBUF
    );
  A_1_IFF_IMUX : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => A_1_INBUF,
      O => A_1_IBUF
    );
  A_2_IFF_IMUX : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => A_2_INBUF,
      O => A_2_IBUF
    );
  A_3_IFF_IMUX : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => A_3_INBUF,
      O => A_3_IBUF
    );
  B_0_IFF_IMUX : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => B_0_INBUF,
      O => B_0_IBUF
    );
  B_1_IFF_IMUX : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => B_1_INBUF,
      O => B_1_IBUF
    );
  B_2_IFF_IMUX : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => B_2_INBUF,
      O => B_2_IBUF
    );
  B_3_IFF_IMUX : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => B_3_INBUF,
      O => B_3_IBUF
    );
  S_0_OUTPUT_OFF_OMUX : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => S_0_OBUF,
      O => S_0_O
    );
  S_1_OUTPUT_OFF_OMUX : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => S_1_OBUF,
      O => S_1_O
    );
  S_2_OUTPUT_OFF_OMUX : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => S_2_OBUF,
      O => S_2_O
    );
  S_3_OUTPUT_OFF_OMUX : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => S_3_OBUF,
      O => S_3_O
    );
  Carry_out_OUTPUT_OFF_OMUX : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => Carry_out_OBUF,
      O => Carry_out_O
    );
  Enable_IFF_IMUX : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => Enable_INBUF,
      O => Enable_IBUF
    );
  NlwBlock_ripple_carry_adder_VCC : X_ONE
    port map (
      O => VCC
    );
  NlwBlockROC : X_ROC
    generic map (ROC_WIDTH => 100 ns)
    port map (O => GSR);
  NlwBlockTOC : X_TOC
    port map (O => GTS);

end Structure;