-- Z:\CAMURATI\ESERCITAZIONE_1
-- VHDL Test Bench created by
-- HDL Bencher 6.1i
-- Fri Mar 02 10:29:29 2007
-- 
-- Notes:
-- 1) This testbench has been automatically generated from
--   your Test Bench Waveform
-- 2) To use this as a user modifiable testbench do the following:
--   - Save it as a file with a .vhd extension (i.e. File->Save As...)
--   - Add it to your project as a testbench source (i.e. Project->Add Source...)
-- 

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_TEXTIO.ALL;
USE STD.TEXTIO.ALL;

ENTITY rca_tester IS
END rca_tester;

ARCHITECTURE testbench_arch OF rca_tester IS
-- If you get a compiler error on the following line,
-- from the menu do Options->Configuration select VHDL 87
FILE RESULTS: TEXT OPEN WRITE_MODE IS "results.txt";
	COMPONENT ripple_carry_adder
		PORT (
			A : In  std_logic_vector (3 DOWNTO 0);
			B : In  std_logic_vector (3 DOWNTO 0);
			Carry_in : In  std_logic;
			Enable : In  std_logic;
			Carry_out : Out  std_logic;
			S : Out  std_logic_vector (3 DOWNTO 0)
		);
	END COMPONENT;

	SIGNAL A : std_logic_vector (3 DOWNTO 0);
	SIGNAL B : std_logic_vector (3 DOWNTO 0);
	SIGNAL Carry_in : std_logic;
	SIGNAL Enable : std_logic;
	SIGNAL Carry_out : std_logic;
	SIGNAL S : std_logic_vector (3 DOWNTO 0);

BEGIN
	UUT : ripple_carry_adder
	PORT MAP (
		A => A,
		B => B,
		Carry_in => Carry_in,
		Enable => Enable,
		Carry_out => Carry_out,
		S => S
	);

	PROCESS
		VARIABLE TX_OUT : LINE;
		VARIABLE TX_ERROR : INTEGER := 0;

		PROCEDURE CHECK_Carry_out(
			next_Carry_out : std_logic;
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			-- If compiler error ("/=" is ambiguous) occurs in the next line of code
			-- change compiler settings to use explicit declarations only
			IF (Carry_out /= next_Carry_out) THEN 
				STD.TEXTIO.write(TX_LOC,string'("Error at time="));
				STD.TEXTIO.write(TX_LOC, TX_TIME);
				STD.TEXTIO.write(TX_LOC,string'("ns Carry_out="));
				IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, Carry_out);
				STD.TEXTIO.write(TX_LOC, string'(", Expected = "));
				IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, next_Carry_out);
				STD.TEXTIO.write(TX_LOC, string'(" "));
				TX_STR(TX_LOC.all'range) := TX_LOC.all;
				STD.TEXTIO.writeline(results, TX_LOC);
				STD.TEXTIO.Deallocate(TX_LOC);
				ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
				TX_ERROR := TX_ERROR + 1;
			END IF;
		END;

		PROCEDURE CHECK_S(
			next_S : std_logic_vector (3 DOWNTO 0);
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			-- If compiler error ("/=" is ambiguous) occurs in the next line of code
			-- change compiler settings to use explicit declarations only
			IF (S /= next_S) THEN 
				STD.TEXTIO.write(TX_LOC,string'("Error at time="));
				STD.TEXTIO.write(TX_LOC, TX_TIME);
				STD.TEXTIO.write(TX_LOC,string'("ns S="));
				IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, S);
				STD.TEXTIO.write(TX_LOC, string'(", Expected = "));
				IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, next_S);
				STD.TEXTIO.write(TX_LOC, string'(" "));
				TX_STR(TX_LOC.all'range) := TX_LOC.all;
				STD.TEXTIO.writeline(results, TX_LOC);
				STD.TEXTIO.Deallocate(TX_LOC);
				ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
				TX_ERROR := TX_ERROR + 1;
			END IF;
		END;

		BEGIN
		-- --------------------
		A <= transport std_logic_vector'("0000"); --0
		B <= transport std_logic_vector'("0000"); --0
		Carry_in <= transport '0';
		Enable <= transport '0';
		-- --------------------
		WAIT FOR 500 ns; -- Time=500 ns
		A <= transport std_logic_vector'("1010"); --A
		B <= transport std_logic_vector'("0001"); --1
		Carry_in <= transport '1';
		Enable <= transport '1';
		-- --------------------
		WAIT FOR 100 ns; -- Time=600 ns
		A <= transport std_logic_vector'("1000"); --8
		B <= transport std_logic_vector'("1111"); --F
		-- --------------------
		WAIT FOR 100 ns; -- Time=700 ns
		A <= transport std_logic_vector'("0100"); --4
		B <= transport std_logic_vector'("1001"); --9
		-- --------------------
		WAIT FOR 100 ns; -- Time=800 ns
		A <= transport std_logic_vector'("0001"); --1
		B <= transport std_logic_vector'("0000"); --0
		-- --------------------
		WAIT FOR 100 ns; -- Time=900 ns
		A <= transport std_logic_vector'("0000"); --0
		B <= transport std_logic_vector'("0100"); --4
		-- --------------------
		WAIT FOR 100 ns; -- Time=1000 ns
		A <= transport std_logic_vector'("1111"); --F
		B <= transport std_logic_vector'("1111"); --F
		-- --------------------
		WAIT FOR 200 ns; -- Time=1200 ns
		Carry_in <= transport '0';
		-- --------------------
		WAIT FOR 150 ns; -- Time=1350 ns
		-- --------------------

		IF (TX_ERROR = 0) THEN 
			STD.TEXTIO.write(TX_OUT,string'("No errors or warnings"));
			STD.TEXTIO.writeline(results, TX_OUT);
			ASSERT (FALSE) REPORT
				"Simulation successful (not a failure).  No problems detected. "
				SEVERITY FAILURE;
		ELSE
			STD.TEXTIO.write(TX_OUT, TX_ERROR);
			STD.TEXTIO.write(TX_OUT, string'(
				" errors found in simulation"));
			STD.TEXTIO.writeline(results, TX_OUT);
			ASSERT (FALSE) REPORT
				"Errors found during simulation"
				SEVERITY FAILURE;
		END IF;
	END PROCESS;
END testbench_arch;

CONFIGURATION ripple_carry_adder_cfg OF rca_tester IS
	FOR testbench_arch
	END FOR;
END ripple_carry_adder_cfg;