## NOTE: Do not edit this file.
## Auto generated by Project Navigator for VHDL Post-PAR Simulation
##
vlib work
## Compile Post-PAR Model for Module ripple_carry_adder
vcom -87 -explicit  ripple_carry_adder_timesim.vhd
vcom -93 -explicit  rca_tester.timesim_vhw
vsim -t 1ps -sdfmax /UUT=ripple_carry_adder_timesim.sdf  -lib work rca_tester
do rca_tester.udo
view wave
add wave *
view structure
view signals
run -all
## End