JDF G
// Created by Project Navigator ver 1.0
PROJECT esercitazione_1
DESIGN esercitazione_1
DEVFAM spartan3
DEVFAMTIME 0
DEVICE xc3s200
DEVICETIME 0
DEVPKG ft256
DEVPKGTIME 0
DEVSPEED -4
DEVSPEEDTIME 0
DEVTOPLEVELMODULETYPE HDL
TOPLEVELMODULETYPETIME 0
DEVSYNTHESISTOOL XST (VHDL/Verilog)
SYNTHESISTOOLTIME 0
DEVSIMULATOR Modelsim
SIMULATORTIME 0
DEVGENERATEDSIMULATIONMODEL VHDL
GENERATEDSIMULATIONMODELTIME 0
SOURCE es_1.vhd
STIMULUS test_fa.tbw
SOURCE ripple_carry_adder.sch
STIMULUS rca_tester.tbw
SOURCE Carry_lookahead_logic.vhd
SOURCE Carry_lookahead_adder.sch
STIMULUS carry_lookahead_tester.tbw
DEPASSOC es_1 es_1.ucf
DEPASSOC ripple_carry_adder ripple_carry_adder.ucf
DEPASSOC carry_lookahead_adder carry_lookahead_adder.ucf
[STATUS-ALL]
carry_lookahead_adder.ngcFile=WARNINGS,1173426810
es_1.ngcFile=WARNINGS,1172823788
ripple_carry_adder.ngcFile=WARNINGS,1172827746
[STRATEGY-LIST]
Normal=True