-- Xilinx Vhdl netlist produced by netgen application (version G.35)
-- Command       : -intstyle ise -s 4 -pcf es_1.pcf -ngm es_1.ngm -rpw 100 -tpw 0 -ar Structure -xon true -w -ofmt vhdl -sim es_1.ncd es_1_timesim.vhd 
-- Input file    : es_1.ncd
-- Output file   : es_1_timesim.vhd
-- Design name   : es_1
-- # of Entities : 1
-- Xilinx        : C:/Program Files/Xilinx
-- Device        : 3s200ft256-4 (PRODUCTION 1.32 2004-06-25)

-- This vhdl netlist is a simulation model and uses simulation 
-- primitives which may not represent the true implementation of the 
-- device, however the netlist is functionally correct and should not 
-- be modified. This file cannot be synthesized and should only be used 
-- with supported simulation tools.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library SIMPRIM;
use SIMPRIM.VCOMPONENTS.ALL;
use SIMPRIM.VPACKAGE.ALL;

entity es_1 is
  port (
    S0 : out STD_LOGIC; 
    C_out : out STD_LOGIC; 
    C_in : in STD_LOGIC := 'X'; 
    B : in STD_LOGIC := 'X'; 
    A : in STD_LOGIC := 'X'; 
    ce : in STD_LOGIC := 'X' 
  );
end es_1;

architecture Structure of es_1 is
  signal C_out_OBUF : STD_LOGIC; 
  signal S0_OBUF : STD_LOGIC; 
  signal C_in_IBUF : STD_LOGIC; 
  signal A_IBUF : STD_LOGIC; 
  signal B_IBUF : STD_LOGIC; 
  signal ce_IBUF : STD_LOGIC; 
  signal GSR : STD_LOGIC; 
  signal GTS : STD_LOGIC; 
  signal C_out_ENABLE : STD_LOGIC; 
  signal C_out_GTS_OR_T : STD_LOGIC; 
  signal C_out_O : STD_LOGIC; 
  signal S0_ENABLE : STD_LOGIC; 
  signal S0_GTS_OR_T : STD_LOGIC; 
  signal S0_O : STD_LOGIC; 
  signal C_in_INBUF : STD_LOGIC; 
  signal A_INBUF : STD_LOGIC; 
  signal B_INBUF : STD_LOGIC; 
  signal ce_INBUF : STD_LOGIC; 
  signal S0_OBUF_F : STD_LOGIC; 
  signal S0_OBUF_G : STD_LOGIC; 
begin
  C_out_OBUF_0 : X_TRI_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => C_out_O,
      CTL => C_out_ENABLE,
      O => C_out
    );
  C_out_ENABLEINV : X_INV
    port map (
      I => C_out_GTS_OR_T,
      O => C_out_ENABLE
    );
  C_out_GTS_OR_T_1 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => GTS,
      O => C_out_GTS_OR_T
    );
  S0_OBUF_2 : X_TRI_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => S0_O,
      CTL => S0_ENABLE,
      O => S0
    );
  S0_ENABLEINV : X_INV
    port map (
      I => S0_GTS_OR_T,
      O => S0_ENABLE
    );
  S0_GTS_OR_T_3 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => GTS,
      O => S0_GTS_OR_T
    );
  C_in_IBUF_4 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => C_in,
      O => C_in_INBUF
    );
  A_IBUF_5 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => A,
      O => A_INBUF
    );
  B_IBUF_6 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => B,
      O => B_INBUF
    );
  ce_IBUF_7 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => ce,
      O => ce_INBUF
    );
  carry_out1 : X_LUT4
    generic map(
      INIT => X"A880"
    )
    port map (
      ADR0 => ce_IBUF,
      ADR1 => A_IBUF,
      ADR2 => B_IBUF,
      ADR3 => C_in_IBUF,
      O => S0_OBUF_G
    );
  S0_OBUF_XUSED : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => S0_OBUF_F,
      O => S0_OBUF
    );
  S0_OBUF_YUSED : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => S0_OBUF_G,
      O => C_out_OBUF
    );
  sum1 : X_LUT4
    generic map(
      INIT => X"8228"
    )
    port map (
      ADR0 => ce_IBUF,
      ADR1 => A_IBUF,
      ADR2 => B_IBUF,
      ADR3 => C_in_IBUF,
      O => S0_OBUF_F
    );
  C_out_OUTPUT_OFF_OMUX : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => C_out_OBUF,
      O => C_out_O
    );
  S0_OUTPUT_OFF_OMUX : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => S0_OBUF,
      O => S0_O
    );
  C_in_IFF_IMUX : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => C_in_INBUF,
      O => C_in_IBUF
    );
  A_IFF_IMUX : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => A_INBUF,
      O => A_IBUF
    );
  B_IFF_IMUX : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => B_INBUF,
      O => B_IBUF
    );
  ce_IFF_IMUX : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => ce_INBUF,
      O => ce_IBUF
    );
  NlwBlockROC : X_ROC
    generic map (ROC_WIDTH => 100 ns)
    port map (O => GSR);
  NlwBlockTOC : X_TOC
    port map (O => GTS);

end Structure;