library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity es_1 is
Port(A:in std_logic;B:in std_logic;C_in:in std_logic;ce:in std_logic;S0:out std_logic;C_out:out std_logic);
end es_1;

architecture Behavioral of es_1 is

signal sum: std_logic:='0';
signal carry_out: std_logic:='0';

begin

process(A,B,C_in)
begin
if ce='0'	  then
	sum<='0';
	carry_out<='0';
else
	sum<=(A xor B)xor C_in;
	carry_out<=(A and B)or(C_in and(A xor B));
end if;
end process;

S0<=sum;
C_out<=carry_out;

end Behavioral;