Release 6.3i Par G.35
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.

LABINF43::  Fri Mar 02 09:46:38 2007


C:/Program Files/Xilinx/bin/nt/par.exe -w -intstyle ise -ol std -t 1
es_1_map.ncd es_1.ncd es_1.pcf 


Constraints file: es_1.pcf

Loading device database for application Par from file "es_1_map.ncd".
   "es_1" is an NCD, version 2.38, device xc3s200, package ft256, speed -4
Loading device for application Par from file '3s200.nph' in environment
C:/Program Files/Xilinx.
Device speed data version:  PRODUCTION 1.32 2004-06-25.


Resolved that IOB <C_out> must be placed at site P14.
Resolved that IOB <S0> must be placed at site K12.
Resolved that IOB <C_in> must be placed at site H14.
Resolved that IOB <A> must be placed at site F12.
Resolved that IOB <B> must be placed at site G12.
Resolved that IOB <ce> must be placed at site H13.


Device utilization summary:

   Number of External IOBs             6 out of 173     3%
      Number of LOCed External IOBs    6 out of 6     100%

   Number of Slices                    1 out of 1920    1%




Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)


Phase 1.1
Phase 1.1 (Checksum:98968d) REAL time: 0 secs 

Phase 3.8
.
Phase 3.8 (Checksum:98a273) REAL time: 0 secs 

Phase 4.5
Phase 4.5 (Checksum:26259fc) REAL time: 0 secs 

Phase 5.18
Phase 5.18 (Checksum:2faf07b) REAL time: 0 secs 

Writing design to file es_1.ncd.

Total REAL time to Placer completion: 0 secs 
Total CPU time to Placer completion: 0 secs 


Phase 1: 10 unrouted;       REAL time: 0 secs 

Phase 2: 10 unrouted;       REAL time: 0 secs 

Phase 3: 0 unrouted;       REAL time: 0 secs 

Phase 4: 0 unrouted;       REAL time: 0 secs 

Total REAL time to Router completion: 0 secs 
Total CPU time to Router completion: 0 secs 

Generating "par" statistics.


   The Delay Summary Report

   The SCORE FOR THIS DESIGN is: 113


The NUMBER OF SIGNALS NOT COMPLETELY ROUTED for this design is: 0

   The AVERAGE CONNECTION DELAY for this design is:        0.994
   The MAXIMUM PIN DELAY IS:                               2.064
   The AVERAGE CONNECTION DELAY on the 10 WORST NETS is:   0.682

   Listing Pin Delays by value: (nsec)

    d < 1.00   < d < 2.00  < d < 3.00  < d < 4.00  < d < 5.00  d >= 5.00
   ---------   ---------   ---------   ---------   ---------   ---------
           6           3           1           0           0           0

Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 5 secs 
Total CPU time to PAR completion: 1 secs 

Peak Memory Usage:  55 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.

Writing design to file es_1.ncd.


PAR done.