-- Z:\CAMURATI\ESERCITAZIONE_1
-- VHDL Test Bench created by
-- HDL Bencher 6.1i
-- Fri Mar 09 09:02:29 2007
-- 
-- Notes:
-- 1) This testbench has been automatically generated from
--   your Test Bench Waveform
-- 2) To use this as a user modifiable testbench do the following:
--   - Save it as a file with a .vhd extension (i.e. File->Save As...)
--   - Add it to your project as a testbench source (i.e. Project->Add Source...)
-- 

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_TEXTIO.ALL;
USE STD.TEXTIO.ALL;

ENTITY carry_lookahead_tester IS
END carry_lookahead_tester;

ARCHITECTURE testbench_arch OF carry_lookahead_tester IS
-- If you get a compiler error on the following line,
-- from the menu do Options->Configuration select VHDL 87
FILE RESULTS: TEXT OPEN WRITE_MODE IS "results.txt";
	COMPONENT carry_lookahead_adder
		PORT (
			A : In  std_logic_vector (3 DOWNTO 0);
			B : In  std_logic_vector (3 DOWNTO 0);
			Carry_in : In  std_logic;
			Enable : In  std_logic;
			S : Out  std_logic_vector (4 DOWNTO 0)
		);
	END COMPONENT;

	SIGNAL A : std_logic_vector (3 DOWNTO 0);
	SIGNAL B : std_logic_vector (3 DOWNTO 0);
	SIGNAL Carry_in : std_logic;
	SIGNAL Enable : std_logic;
	SIGNAL S : std_logic_vector (4 DOWNTO 0);

BEGIN
	UUT : carry_lookahead_adder
	PORT MAP (
		A => A,
		B => B,
		Carry_in => Carry_in,
		Enable => Enable,
		S => S
	);

	PROCESS
		VARIABLE TX_OUT : LINE;
		VARIABLE TX_ERROR : INTEGER := 0;

		PROCEDURE CHECK_S(
			next_S : std_logic_vector (4 DOWNTO 0);
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			-- If compiler error ("/=" is ambiguous) occurs in the next line of code
			-- change compiler settings to use explicit declarations only
			IF (S /= next_S) THEN 
				STD.TEXTIO.write(TX_LOC,string'("Error at time="));
				STD.TEXTIO.write(TX_LOC, TX_TIME);
				STD.TEXTIO.write(TX_LOC,string'("ms S="));
				IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, S);
				STD.TEXTIO.write(TX_LOC, string'(", Expected = "));
				IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, next_S);
				STD.TEXTIO.write(TX_LOC, string'(" "));
				TX_STR(TX_LOC.all'range) := TX_LOC.all;
				STD.TEXTIO.writeline(results, TX_LOC);
				STD.TEXTIO.Deallocate(TX_LOC);
				ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
				TX_ERROR := TX_ERROR + 1;
			END IF;
		END;

		BEGIN
		-- --------------------
		A <= transport std_logic_vector'("0000"); --0
		B <= transport std_logic_vector'("0000"); --0
		Carry_in <= transport '0';
		Enable <= transport '0';
		-- --------------------
		WAIT FOR 50 ms; -- Time=50 ms
		CHECK_S("00000",50); --0
		-- --------------------
		WAIT FOR 50 ms; -- Time=100 ms
		A <= transport std_logic_vector'("0011"); --3
		B <= transport std_logic_vector'("0100"); --4
		-- --------------------
		WAIT FOR 50 ms; -- Time=150 ms
		CHECK_S("00000",150); --0
		-- --------------------
		WAIT FOR 50 ms; -- Time=200 ms
		A <= transport std_logic_vector'("0110"); --6
		B <= transport std_logic_vector'("1011"); --B
		Carry_in <= transport '0';
		-- --------------------
		WAIT FOR 50 ms; -- Time=250 ms
		CHECK_S("00000",250); --0
		-- --------------------
		WAIT FOR 50 ms; -- Time=300 ms
		Carry_in <= transport '0';
		-- --------------------
		WAIT FOR 50 ms; -- Time=350 ms
		CHECK_S("00000",350); --0
		-- --------------------
		WAIT FOR 50 ms; -- Time=400 ms
		A <= transport std_logic_vector'("0101"); --5
		B <= transport std_logic_vector'("0110"); --6
		-- --------------------
		WAIT FOR 50 ms; -- Time=450 ms
		CHECK_S("00000",450); --0
		-- --------------------
		WAIT FOR 50 ms; -- Time=500 ms
		Enable <= transport '1';
		-- --------------------
		WAIT FOR 50 ms; -- Time=550 ms
		CHECK_S("00011",550); --3
		-- --------------------
		WAIT FOR 50 ms; -- Time=600 ms
		A <= transport std_logic_vector'("1010"); --A
		B <= transport std_logic_vector'("0001"); --1
		-- --------------------
		WAIT FOR 50 ms; -- Time=650 ms
		CHECK_S("UUUU0",650); --U?
		-- --------------------
		WAIT FOR 50 ms; -- Time=700 ms
		A <= transport std_logic_vector'("1100"); --C
		B <= transport std_logic_vector'("0000"); --0
		Carry_in <= transport '0';
		-- --------------------
		WAIT FOR 50 ms; -- Time=750 ms
		CHECK_S("01011",750); --B
		-- --------------------
		WAIT FOR 50 ms; -- Time=800 ms
		A <= transport std_logic_vector'("0100"); --4
		B <= transport std_logic_vector'("1001"); --9
		-- --------------------
		WAIT FOR 50 ms; -- Time=850 ms
		CHECK_S("01100",850); --C
		-- --------------------
		WAIT FOR 50 ms; -- Time=900 ms
		A <= transport std_logic_vector'("0010"); --2
		B <= transport std_logic_vector'("1000"); --8
		-- --------------------
		WAIT FOR 50 ms; -- Time=950 ms
		CHECK_S("01001",950); --9
		-- --------------------
		WAIT FOR 100 ms; -- Time=1050 ms
		CHECK_S("01001",1050); --9
		-- --------------------
		WAIT FOR 100 ms; -- Time=1150 ms
		CHECK_S("00000",1150); --0
		-- --------------------
		WAIT FOR 150 ms; -- Time=1300 ms
		Enable <= transport '0';
		-- --------------------
		WAIT FOR 150 ms; -- Time=1450 ms
		-- --------------------

		IF (TX_ERROR = 0) THEN 
			STD.TEXTIO.write(TX_OUT,string'("No errors or warnings"));
			STD.TEXTIO.writeline(results, TX_OUT);
			ASSERT (FALSE) REPORT
				"Simulation successful (not a failure).  No problems detected. "
				SEVERITY FAILURE;
		ELSE
			STD.TEXTIO.write(TX_OUT, TX_ERROR);
			STD.TEXTIO.write(TX_OUT, string'(
				" errors found in simulation"));
			STD.TEXTIO.writeline(results, TX_OUT);
			ASSERT (FALSE) REPORT
				"Errors found during simulation"
				SEVERITY FAILURE;
		END IF;
	END PROCESS;
END testbench_arch;

CONFIGURATION carry_lookahead_adder_cfg OF carry_lookahead_tester IS
	FOR testbench_arch
	END FOR;
END carry_lookahead_adder_cfg;