-- Xilinx Vhdl netlist produced by netgen application (version G.35)
-- Command       : -intstyle ise -s 4 -pcf carry_lookahead_adder.pcf -ngm carry_lookahead_adder.ngm -rpw 100 -tpw 0 -ar Structure -xon true -w -ofmt vhdl -sim carry_lookahead_adder.ncd carry_lookahead_adder_timesim.vhd 
-- Input file    : carry_lookahead_adder.ncd
-- Output file   : carry_lookahead_adder_timesim.vhd
-- Design name   : carry_lookahead_adder
-- # of Entities : 1
-- Xilinx        : C:/Program Files/Xilinx
-- Device        : 3s200ft256-4 (PRODUCTION 1.32 2004-06-25)

-- This vhdl netlist is a simulation model and uses simulation 
-- primitives which may not represent the true implementation of the 
-- device, however the netlist is functionally correct and should not 
-- be modified. This file cannot be synthesized and should only be used 
-- with supported simulation tools.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library SIMPRIM;
use SIMPRIM.VCOMPONENTS.ALL;
use SIMPRIM.VPACKAGE.ALL;

entity carry_lookahead_adder is
  port (
    Carry_in : in STD_LOGIC := 'X'; 
    Enable : in STD_LOGIC := 'X'; 
    S : out STD_LOGIC_VECTOR ( 4 downto 0 ); 
    B : in STD_LOGIC_VECTOR ( 3 downto 0 ); 
    A : in STD_LOGIC_VECTOR ( 3 downto 0 ) 
  );
end carry_lookahead_adder;

architecture Structure of carry_lookahead_adder is
  signal Carry_in_IBUF : STD_LOGIC; 
  signal A_0_IBUF : STD_LOGIC; 
  signal A_1_IBUF : STD_LOGIC; 
  signal A_2_IBUF : STD_LOGIC; 
  signal A_3_IBUF : STD_LOGIC; 
  signal B_0_IBUF : STD_LOGIC; 
  signal B_1_IBUF : STD_LOGIC; 
  signal B_2_IBUF : STD_LOGIC; 
  signal B_3_IBUF : STD_LOGIC; 
  signal S_0_OBUF : STD_LOGIC; 
  signal S_1_OBUF : STD_LOGIC; 
  signal S_2_OBUF : STD_LOGIC; 
  signal S_3_OBUF : STD_LOGIC; 
  signal S_4_OBUF : STD_LOGIC; 
  signal Enable_BUFGP_IBUFG : STD_LOGIC; 
  signal GLOBAL_LOGIC1 : STD_LOGIC; 
  signal Enable_BUFGP : STD_LOGIC; 
  signal N1241 : STD_LOGIC; 
  signal N1208 : STD_LOGIC; 
  signal XLXI_1_N476 : STD_LOGIC; 
  signal GSR : STD_LOGIC; 
  signal GTS : STD_LOGIC; 
  signal Carry_in_INBUF : STD_LOGIC; 
  signal A_0_INBUF : STD_LOGIC; 
  signal A_1_INBUF : STD_LOGIC; 
  signal A_2_INBUF : STD_LOGIC; 
  signal A_3_INBUF : STD_LOGIC; 
  signal B_0_INBUF : STD_LOGIC; 
  signal B_1_INBUF : STD_LOGIC; 
  signal B_2_INBUF : STD_LOGIC; 
  signal B_3_INBUF : STD_LOGIC; 
  signal S_0_ENABLE : STD_LOGIC; 
  signal S_0_GTS_OR_T : STD_LOGIC; 
  signal S_0_O : STD_LOGIC; 
  signal S_1_ENABLE : STD_LOGIC; 
  signal S_1_GTS_OR_T : STD_LOGIC; 
  signal S_1_O : STD_LOGIC; 
  signal S_2_ENABLE : STD_LOGIC; 
  signal S_2_GTS_OR_T : STD_LOGIC; 
  signal S_2_O : STD_LOGIC; 
  signal S_3_ENABLE : STD_LOGIC; 
  signal S_3_GTS_OR_T : STD_LOGIC; 
  signal S_3_O : STD_LOGIC; 
  signal S_4_ENABLE : STD_LOGIC; 
  signal S_4_GTS_OR_T : STD_LOGIC; 
  signal S_4_O : STD_LOGIC; 
  signal Enable_INBUF : STD_LOGIC; 
  signal Enable_BUFGP_BUFG_S_INVNOT : STD_LOGIC; 
  signal XLXI_1_G_1_DXMUX : STD_LOGIC; 
  signal XLXI_1_n0001 : STD_LOGIC; 
  signal XLXI_1_G_1_DYMUX : STD_LOGIC; 
  signal XLXI_1_n0000 : STD_LOGIC; 
  signal XLXI_1_G_1_CLKINVNOT : STD_LOGIC; 
  signal XLXI_1_G_3_DXMUX : STD_LOGIC; 
  signal XLXI_1_n0003 : STD_LOGIC; 
  signal XLXI_1_G_3_DYMUX : STD_LOGIC; 
  signal XLXI_1_n0002 : STD_LOGIC; 
  signal XLXI_1_G_3_CLKINVNOT : STD_LOGIC; 
  signal XLXI_1_P_1_DXMUX : STD_LOGIC; 
  signal XLXI_1_n0005 : STD_LOGIC; 
  signal XLXI_1_P_1_DYMUX : STD_LOGIC; 
  signal XLXI_1_n0004 : STD_LOGIC; 
  signal XLXI_1_P_1_CLKINVNOT : STD_LOGIC; 
  signal XLXI_1_P_3_DXMUX : STD_LOGIC; 
  signal XLXI_1_n0007 : STD_LOGIC; 
  signal XLXI_1_P_3_DYMUX : STD_LOGIC; 
  signal XLXI_1_n0006 : STD_LOGIC; 
  signal XLXI_1_P_3_CLKINVNOT : STD_LOGIC; 
  signal N1241_F : STD_LOGIC; 
  signal N1241_G : STD_LOGIC; 
  signal S_1_OBUF_F : STD_LOGIC; 
  signal S_1_OBUF_G : STD_LOGIC; 
  signal S_3_OBUF_F : STD_LOGIC; 
  signal S_3_OBUF_G : STD_LOGIC; 
  signal S_4_OBUF_F : STD_LOGIC; 
  signal S_4_OBUF_G : STD_LOGIC; 
  signal S_2_OBUF_F : STD_LOGIC; 
  signal S_2_OBUF_G : STD_LOGIC; 
  signal XLXI_1_G_1_FFX_RST : STD_LOGIC; 
  signal XLXI_1_G_3_FFY_RST : STD_LOGIC; 
  signal XLXI_1_G_3_FFX_RST : STD_LOGIC; 
  signal XLXI_1_P_1_FFY_RST : STD_LOGIC; 
  signal XLXI_1_P_1_FFX_RST : STD_LOGIC; 
  signal XLXI_1_P_3_FFY_RST : STD_LOGIC; 
  signal XLXI_1_P_3_FFX_RST : STD_LOGIC; 
  signal XLXI_1_G_1_FFY_RST : STD_LOGIC; 
  signal GND : STD_LOGIC; 
  signal VCC : STD_LOGIC; 
  signal NlwInverterSignal_XLXI_1_G_1_CLK : STD_LOGIC; 
  signal NlwInverterSignal_XLXI_1_G_2_CLK : STD_LOGIC; 
  signal NlwInverterSignal_XLXI_1_G_3_CLK : STD_LOGIC; 
  signal NlwInverterSignal_XLXI_1_P_0_CLK : STD_LOGIC; 
  signal NlwInverterSignal_XLXI_1_P_1_CLK : STD_LOGIC; 
  signal NlwInverterSignal_XLXI_1_P_2_CLK : STD_LOGIC; 
  signal NlwInverterSignal_XLXI_1_P_3_CLK : STD_LOGIC; 
  signal NlwInverterSignal_XLXI_1_G_0_CLK : STD_LOGIC; 
  signal XLXI_1_G : STD_LOGIC_VECTOR ( 3 downto 0 ); 
  signal XLXI_1_P : STD_LOGIC_VECTOR ( 3 downto 0 ); 
  signal C : STD_LOGIC_VECTOR ( 2 downto 1 ); 
begin
  Carry_in_IBUF_0 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => Carry_in,
      O => Carry_in_INBUF
    );
  A_0_IBUF_1 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => A(0),
      O => A_0_INBUF
    );
  A_1_IBUF_2 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => A(1),
      O => A_1_INBUF
    );
  A_2_IBUF_3 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => A(2),
      O => A_2_INBUF
    );
  A_3_IBUF_4 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => A(3),
      O => A_3_INBUF
    );
  B_0_IBUF_5 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => B(0),
      O => B_0_INBUF
    );
  B_1_IBUF_6 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => B(1),
      O => B_1_INBUF
    );
  B_2_IBUF_7 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => B(2),
      O => B_2_INBUF
    );
  B_3_IBUF_8 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => B(3),
      O => B_3_INBUF
    );
  S_0_OBUF_9 : X_TRI_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => S_0_O,
      CTL => S_0_ENABLE,
      O => S(0)
    );
  S_0_ENABLEINV : X_INV
    port map (
      I => S_0_GTS_OR_T,
      O => S_0_ENABLE
    );
  S_0_GTS_OR_T_10 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => GTS,
      O => S_0_GTS_OR_T
    );
  S_1_OBUF_11 : X_TRI_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => S_1_O,
      CTL => S_1_ENABLE,
      O => S(1)
    );
  S_1_ENABLEINV : X_INV
    port map (
      I => S_1_GTS_OR_T,
      O => S_1_ENABLE
    );
  S_1_GTS_OR_T_12 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => GTS,
      O => S_1_GTS_OR_T
    );
  S_2_OBUF_13 : X_TRI_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => S_2_O,
      CTL => S_2_ENABLE,
      O => S(2)
    );
  S_2_ENABLEINV : X_INV
    port map (
      I => S_2_GTS_OR_T,
      O => S_2_ENABLE
    );
  S_2_GTS_OR_T_14 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => GTS,
      O => S_2_GTS_OR_T
    );
  S_3_OBUF_15 : X_TRI_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => S_3_O,
      CTL => S_3_ENABLE,
      O => S(3)
    );
  S_3_ENABLEINV : X_INV
    port map (
      I => S_3_GTS_OR_T,
      O => S_3_ENABLE
    );
  S_3_GTS_OR_T_16 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => GTS,
      O => S_3_GTS_OR_T
    );
  S_4_OBUF_17 : X_TRI_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => S_4_O,
      CTL => S_4_ENABLE,
      O => S(4)
    );
  S_4_ENABLEINV : X_INV
    port map (
      I => S_4_GTS_OR_T,
      O => S_4_ENABLE
    );
  S_4_GTS_OR_T_18 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => GTS,
      O => S_4_GTS_OR_T
    );
  Enable_BUFGP_IBUFG_19 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => Enable,
      O => Enable_INBUF
    );
  Enable_BUFGP_BUFG : X_BUFGMUX
    port map (
      I0 => Enable_BUFGP_IBUFG,
      I1 => GND,
      S => Enable_BUFGP_BUFG_S_INVNOT,
      O => Enable_BUFGP,
      GSR => GSR
    );
  Enable_BUFGP_BUFG_SINV : X_INV
    port map (
      I => GLOBAL_LOGIC1,
      O => Enable_BUFGP_BUFG_S_INVNOT
    );
  XLXI_1_G_1_DXMUX_20 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => XLXI_1_n0001,
      O => XLXI_1_G_1_DXMUX
    );
  XLXI_1_G_1_DYMUX_21 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => XLXI_1_n0000,
      O => XLXI_1_G_1_DYMUX
    );
  XLXI_1_G_1_CLKINV : X_INV
    port map (
      I => Enable_BUFGP,
      O => XLXI_1_G_1_CLKINVNOT
    );
  XLXI_1_G_3_DXMUX_22 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => XLXI_1_n0003,
      O => XLXI_1_G_3_DXMUX
    );
  XLXI_1_G_3_DYMUX_23 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => XLXI_1_n0002,
      O => XLXI_1_G_3_DYMUX
    );
  XLXI_1_G_3_CLKINV : X_INV
    port map (
      I => Enable_BUFGP,
      O => XLXI_1_G_3_CLKINVNOT
    );
  XLXI_1_P_1_DXMUX_24 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => XLXI_1_n0005,
      O => XLXI_1_P_1_DXMUX
    );
  XLXI_1_P_1_DYMUX_25 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => XLXI_1_n0004,
      O => XLXI_1_P_1_DYMUX
    );
  XLXI_1_P_1_CLKINV : X_INV
    port map (
      I => Enable_BUFGP,
      O => XLXI_1_P_1_CLKINVNOT
    );
  XLXI_1_P_3_DXMUX_26 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => XLXI_1_n0007,
      O => XLXI_1_P_3_DXMUX
    );
  XLXI_1_P_3_DYMUX_27 : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => XLXI_1_n0006,
      O => XLXI_1_P_3_DYMUX
    );
  XLXI_1_P_3_CLKINV : X_INV
    port map (
      I => Enable_BUFGP,
      O => XLXI_1_P_3_CLKINVNOT
    );
  XLXI_1_n0032_SW0 : X_LUT4
    generic map(
      INIT => X"EEAA"
    )
    port map (
      ADR0 => XLXI_1_G(0),
      ADR1 => XLXI_1_P(0),
      ADR2 => VCC,
      ADR3 => Carry_in_IBUF,
      O => N1241_G
    );
  N1241_XUSED : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => N1241_F,
      O => N1241
    );
  N1241_YUSED : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => N1241_G,
      O => N1208
    );
  S_1_OBUF_XUSED : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => S_1_OBUF_F,
      O => S_1_OBUF
    );
  S_1_OBUF_YUSED : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => S_1_OBUF_G,
      O => C(1)
    );
  S_3_OBUF_XUSED : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => S_3_OBUF_F,
      O => S_3_OBUF
    );
  S_3_OBUF_YUSED : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => S_3_OBUF_G,
      O => XLXI_1_N476
    );
  S_4_OBUF_XUSED : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => S_4_OBUF_F,
      O => S_4_OBUF
    );
  S_4_OBUF_YUSED : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => S_4_OBUF_G,
      O => S_0_OBUF
    );
  S_2_OBUF_XUSED : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => S_2_OBUF_F,
      O => S_2_OBUF
    );
  S_2_OBUF_YUSED : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => S_2_OBUF_G,
      O => C(2)
    );
  XLXI_1_n00011 : X_LUT4
    generic map(
      INIT => X"C0C0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => A_1_IBUF,
      ADR2 => B_1_IBUF,
      ADR3 => VCC,
      O => XLXI_1_n0001
    );
  XLXI_1_G_1 : X_LATCHE
    generic map(
      INIT => '0'
    )
    port map (
      I => XLXI_1_G_1_DXMUX,
      GE => VCC,
      CLK => NlwInverterSignal_XLXI_1_G_1_CLK,
      SET => GND,
      RST => XLXI_1_G_1_FFX_RST,
      O => XLXI_1_G(1)
    );
  XLXI_1_G_1_FFX_RSTOR : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => GSR,
      O => XLXI_1_G_1_FFX_RST
    );
  XLXI_1_n00041 : X_LUT4
    generic map(
      INIT => X"FFF0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => B_0_IBUF,
      ADR3 => A_0_IBUF,
      O => XLXI_1_n0004
    );
  XLXI_1_G_2 : X_LATCHE
    generic map(
      INIT => '0'
    )
    port map (
      I => XLXI_1_G_3_DYMUX,
      GE => VCC,
      CLK => NlwInverterSignal_XLXI_1_G_2_CLK,
      SET => GND,
      RST => XLXI_1_G_3_FFY_RST,
      O => XLXI_1_G(2)
    );
  XLXI_1_G_3_FFY_RSTOR : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => GSR,
      O => XLXI_1_G_3_FFY_RST
    );
  XLXI_1_n00031 : X_LUT4
    generic map(
      INIT => X"AA00"
    )
    port map (
      ADR0 => A_3_IBUF,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => B_3_IBUF,
      O => XLXI_1_n0003
    );
  XLXI_1_G_3 : X_LATCHE
    generic map(
      INIT => '0'
    )
    port map (
      I => XLXI_1_G_3_DXMUX,
      GE => VCC,
      CLK => NlwInverterSignal_XLXI_1_G_3_CLK,
      SET => GND,
      RST => XLXI_1_G_3_FFX_RST,
      O => XLXI_1_G(3)
    );
  XLXI_1_G_3_FFX_RSTOR : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => GSR,
      O => XLXI_1_G_3_FFX_RST
    );
  XLXI_1_P_0 : X_LATCHE
    generic map(
      INIT => '0'
    )
    port map (
      I => XLXI_1_P_1_DYMUX,
      GE => VCC,
      CLK => NlwInverterSignal_XLXI_1_P_0_CLK,
      SET => GND,
      RST => XLXI_1_P_1_FFY_RST,
      O => XLXI_1_P(0)
    );
  XLXI_1_P_1_FFY_RSTOR : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => GSR,
      O => XLXI_1_P_1_FFY_RST
    );
  XLXI_1_n00051 : X_LUT4
    generic map(
      INIT => X"FAFA"
    )
    port map (
      ADR0 => B_1_IBUF,
      ADR1 => VCC,
      ADR2 => A_1_IBUF,
      ADR3 => VCC,
      O => XLXI_1_n0005
    );
  XLXI_1_n00061 : X_LUT4
    generic map(
      INIT => X"FFF0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => B_2_IBUF,
      ADR3 => A_2_IBUF,
      O => XLXI_1_n0006
    );
  XLXI_13 : X_LUT4
    generic map(
      INIT => X"C888"
    )
    port map (
      ADR0 => XLXI_1_G(3),
      ADR1 => Enable_BUFGP,
      ADR2 => XLXI_1_N476,
      ADR3 => XLXI_1_P(3),
      O => S_4_OBUF_F
    );
  XLXI_10 : X_LUT4
    generic map(
      INIT => X"9060"
    )
    port map (
      ADR0 => A_2_IBUF,
      ADR1 => B_2_IBUF,
      ADR2 => Enable_BUFGP,
      ADR3 => C(2),
      O => S_2_OBUF_F
    );
  XLXI_1_P_1 : X_LATCHE
    generic map(
      INIT => '0'
    )
    port map (
      I => XLXI_1_P_1_DXMUX,
      GE => VCC,
      CLK => NlwInverterSignal_XLXI_1_P_1_CLK,
      SET => GND,
      RST => XLXI_1_P_1_FFX_RST,
      O => XLXI_1_P(1)
    );
  XLXI_1_P_1_FFX_RSTOR : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => GSR,
      O => XLXI_1_P_1_FFX_RST
    );
  XLXI_1_P_2 : X_LATCHE
    generic map(
      INIT => '0'
    )
    port map (
      I => XLXI_1_P_3_DYMUX,
      GE => VCC,
      CLK => NlwInverterSignal_XLXI_1_P_2_CLK,
      SET => GND,
      RST => XLXI_1_P_3_FFY_RST,
      O => XLXI_1_P(2)
    );
  XLXI_1_P_3_FFY_RSTOR : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => GSR,
      O => XLXI_1_P_3_FFY_RST
    );
  XLXI_1_n00071 : X_LUT4
    generic map(
      INIT => X"FFAA"
    )
    port map (
      ADR0 => A_3_IBUF,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => B_3_IBUF,
      O => XLXI_1_n0007
    );
  XLXI_1_P_3 : X_LATCHE
    generic map(
      INIT => '0'
    )
    port map (
      I => XLXI_1_P_3_DXMUX,
      GE => VCC,
      CLK => NlwInverterSignal_XLXI_1_P_3_CLK,
      SET => GND,
      RST => XLXI_1_P_3_FFX_RST,
      O => XLXI_1_P(3)
    );
  XLXI_1_P_3_FFX_RSTOR : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => GSR,
      O => XLXI_1_P_3_FFX_RST
    );
  XLXI_1_Ker474_SW0 : X_LUT4
    generic map(
      INIT => X"E0A0"
    )
    port map (
      ADR0 => XLXI_1_G(0),
      ADR1 => XLXI_1_P(0),
      ADR2 => XLXI_1_P(1),
      ADR3 => Carry_in_IBUF,
      O => N1241_F
    );
  XLXI_1_n0032 : X_LUT4
    generic map(
      INIT => X"E0C0"
    )
    port map (
      ADR0 => N1208,
      ADR1 => XLXI_1_G(1),
      ADR2 => Enable_BUFGP,
      ADR3 => XLXI_1_P(1),
      O => S_2_OBUF_G
    );
  XLXI_1_n00331 : X_LUT4
    generic map(
      INIT => X"E0A0"
    )
    port map (
      ADR0 => XLXI_1_G(0),
      ADR1 => XLXI_1_P(0),
      ADR2 => Enable_BUFGP,
      ADR3 => Carry_in_IBUF,
      O => S_1_OBUF_G
    );
  XLXI_1_Ker474 : X_LUT4
    generic map(
      INIT => X"FFC8"
    )
    port map (
      ADR0 => XLXI_1_G(1),
      ADR1 => XLXI_1_P(2),
      ADR2 => N1241,
      ADR3 => XLXI_1_G(2),
      O => S_3_OBUF_G
    );
  XLXI_11 : X_LUT4
    generic map(
      INIT => X"9060"
    )
    port map (
      ADR0 => B_1_IBUF,
      ADR1 => A_1_IBUF,
      ADR2 => Enable_BUFGP,
      ADR3 => C(1),
      O => S_1_OBUF_F
    );
  XLXI_12 : X_LUT4
    generic map(
      INIT => X"8448"
    )
    port map (
      ADR0 => Carry_in_IBUF,
      ADR1 => Enable_BUFGP,
      ADR2 => B_0_IBUF,
      ADR3 => A_0_IBUF,
      O => S_4_OBUF_G
    );
  XLXI_9 : X_LUT4
    generic map(
      INIT => X"8448"
    )
    port map (
      ADR0 => B_3_IBUF,
      ADR1 => Enable_BUFGP,
      ADR2 => XLXI_1_N476,
      ADR3 => A_3_IBUF,
      O => S_3_OBUF_F
    );
  XLXI_1_n00001 : X_LUT4
    generic map(
      INIT => X"F000"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => B_0_IBUF,
      ADR3 => A_0_IBUF,
      O => XLXI_1_n0000
    );
  XLXI_1_n00021 : X_LUT4
    generic map(
      INIT => X"A0A0"
    )
    port map (
      ADR0 => A_2_IBUF,
      ADR1 => VCC,
      ADR2 => B_2_IBUF,
      ADR3 => VCC,
      O => XLXI_1_n0002
    );
  XLXI_1_G_0 : X_LATCHE
    generic map(
      INIT => '0'
    )
    port map (
      I => XLXI_1_G_1_DYMUX,
      GE => VCC,
      CLK => NlwInverterSignal_XLXI_1_G_0_CLK,
      SET => GND,
      RST => XLXI_1_G_1_FFY_RST,
      O => XLXI_1_G(0)
    );
  XLXI_1_G_1_FFY_RSTOR : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => GSR,
      O => XLXI_1_G_1_FFY_RST
    );
  PWR_VCC_0_LOGICAL_ONE : X_ONE
    port map (
      O => GLOBAL_LOGIC1
    );
  Carry_in_IFF_IMUX : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => Carry_in_INBUF,
      O => Carry_in_IBUF
    );
  A_0_IFF_IMUX : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => A_0_INBUF,
      O => A_0_IBUF
    );
  A_1_IFF_IMUX : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => A_1_INBUF,
      O => A_1_IBUF
    );
  A_2_IFF_IMUX : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => A_2_INBUF,
      O => A_2_IBUF
    );
  A_3_IFF_IMUX : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => A_3_INBUF,
      O => A_3_IBUF
    );
  B_0_IFF_IMUX : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => B_0_INBUF,
      O => B_0_IBUF
    );
  B_1_IFF_IMUX : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => B_1_INBUF,
      O => B_1_IBUF
    );
  B_2_IFF_IMUX : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => B_2_INBUF,
      O => B_2_IBUF
    );
  B_3_IFF_IMUX : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => B_3_INBUF,
      O => B_3_IBUF
    );
  S_0_OUTPUT_OFF_OMUX : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => S_0_OBUF,
      O => S_0_O
    );
  S_1_OUTPUT_OFF_OMUX : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => S_1_OBUF,
      O => S_1_O
    );
  S_2_OUTPUT_OFF_OMUX : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => S_2_OBUF,
      O => S_2_O
    );
  S_3_OUTPUT_OFF_OMUX : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => S_3_OBUF,
      O => S_3_O
    );
  S_4_OUTPUT_OFF_OMUX : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => S_4_OBUF,
      O => S_4_O
    );
  Enable_IFF_IMUX : X_BUF_PP
    generic map(
      PATHPULSE => 757 ps
    )
    port map (
      I => Enable_INBUF,
      O => Enable_BUFGP_IBUFG
    );
  NlwBlock_carry_lookahead_adder_GND : X_ZERO
    port map (
      O => GND
    );
  NlwBlock_carry_lookahead_adder_VCC : X_ONE
    port map (
      O => VCC
    );
  NlwInverterBlock_XLXI_1_G_1_CLK : X_INV
    port map (
      I => XLXI_1_G_1_CLKINVNOT,
      O => NlwInverterSignal_XLXI_1_G_1_CLK
    );
  NlwInverterBlock_XLXI_1_G_2_CLK : X_INV
    port map (
      I => XLXI_1_G_3_CLKINVNOT,
      O => NlwInverterSignal_XLXI_1_G_2_CLK
    );
  NlwInverterBlock_XLXI_1_G_3_CLK : X_INV
    port map (
      I => XLXI_1_G_3_CLKINVNOT,
      O => NlwInverterSignal_XLXI_1_G_3_CLK
    );
  NlwInverterBlock_XLXI_1_P_0_CLK : X_INV
    port map (
      I => XLXI_1_P_1_CLKINVNOT,
      O => NlwInverterSignal_XLXI_1_P_0_CLK
    );
  NlwInverterBlock_XLXI_1_P_1_CLK : X_INV
    port map (
      I => XLXI_1_P_1_CLKINVNOT,
      O => NlwInverterSignal_XLXI_1_P_1_CLK
    );
  NlwInverterBlock_XLXI_1_P_2_CLK : X_INV
    port map (
      I => XLXI_1_P_3_CLKINVNOT,
      O => NlwInverterSignal_XLXI_1_P_2_CLK
    );
  NlwInverterBlock_XLXI_1_P_3_CLK : X_INV
    port map (
      I => XLXI_1_P_3_CLKINVNOT,
      O => NlwInverterSignal_XLXI_1_P_3_CLK
    );
  NlwInverterBlock_XLXI_1_G_0_CLK : X_INV
    port map (
      I => XLXI_1_G_1_CLKINVNOT,
      O => NlwInverterSignal_XLXI_1_G_0_CLK
    );
  NlwBlockROC : X_ROC
    generic map (ROC_WIDTH => 100 ns)
    port map (O => GSR);
  NlwBlockTOC : X_TOC
    port map (O => GTS);

end Structure;