Release 6.3i Par G.35
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.

LABINF43::  Fri Mar 09 09:11:56 2007


C:/Program Files/Xilinx/bin/nt/par.exe -w -intstyle ise -ol std -t 1
carry_lookahead_adder_map.ncd carry_lookahead_adder.ncd
carry_lookahead_adder.pcf 


Constraints file: carry_lookahead_adder.pcf

Loading device database for application Par from file
"carry_lookahead_adder_map.ncd".
   "carry_lookahead_adder" is an NCD, version 2.38, device xc3s200, package
ft256, speed -4
Loading device for application Par from file '3s200.nph' in environment
C:/Program Files/Xilinx.
Device speed data version:  PRODUCTION 1.32 2004-06-25.


Resolved that IOB <Carry_in> must be placed at site M13.
Resolved that IOB <A<0>> must be placed at site F12.
Resolved that IOB <A<1>> must be placed at site G12.
Resolved that IOB <A<2>> must be placed at site H14.
Resolved that IOB <A<3>> must be placed at site H13.
Resolved that IOB <B<0>> must be placed at site J14.
Resolved that IOB <B<1>> must be placed at site J13.
Resolved that IOB <B<2>> must be placed at site K14.
Resolved that IOB <B<3>> must be placed at site K13.
Resolved that IOB <S<0>> must be placed at site K12.
Resolved that IOB <S<1>> must be placed at site P14.
Resolved that IOB <S<2>> must be placed at site L12.
Resolved that IOB <S<3>> must be placed at site N14.
Resolved that IOB <S<4>> must be placed at site P13.
Resolved that IOB <Enable> must be placed at site L14.


Device utilization summary:

   Number of External IOBs            15 out of 173     8%
      Number of LOCed External IOBs   15 out of 15    100%

   Number of Slices                    9 out of 1920    1%

   Number of BUFGMUXs                  1 out of 8      12%



Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)


Phase 1.1
Phase 1.1 (Checksum:9896ca) REAL time: 0 secs 

.....
.........
Phase 3.8
.
Phase 3.8 (Checksum:98ba5b) REAL time: 0 secs 

Phase 4.5
Phase 4.5 (Checksum:26259fc) REAL time: 0 secs 

Phase 5.18
Phase 5.18 (Checksum:2faf07b) REAL time: 0 secs 

Writing design to file carry_lookahead_adder.ncd.

Total REAL time to Placer completion: 0 secs 
Total CPU time to Placer completion: 0 secs 


Phase 1: 66 unrouted;       REAL time: 0 secs 

Phase 2: 62 unrouted;       REAL time: 0 secs 

Phase 3: 22 unrouted;       REAL time: 0 secs 

Phase 4: 0 unrouted;       REAL time: 0 secs 

Total REAL time to Router completion: 0 secs 
Total CPU time to Router completion: 0 secs 

Generating "par" statistics.

**************************
Generating Clock Report
**************************

+-------------------------+----------+------+------+------------+-------------+
|        Clock Net        | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+-------------------------+----------+------+------+------------+-------------+
|      Enable_BUFGP       |  BUFGMUX0| No   |   11 |  0.001     |  1.012      |
+-------------------------+----------+------+------+------------+-------------+


   The Delay Summary Report

   The SCORE FOR THIS DESIGN is: 145


The NUMBER OF SIGNALS NOT COMPLETELY ROUTED for this design is: 0

   The AVERAGE CONNECTION DELAY for this design is:        1.095
   The MAXIMUM PIN DELAY IS:                               3.474
   The AVERAGE CONNECTION DELAY on the 10 WORST NETS is:   1.777

   Listing Pin Delays by value: (nsec)

    d < 1.00   < d < 2.00  < d < 3.00  < d < 4.00  < d < 5.00  d >= 5.00
   ---------   ---------   ---------   ---------   ---------   ---------
          29          29           7           1           0           0

Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 5 secs 
Total CPU time to PAR completion: 1 secs 

Peak Memory Usage:  56 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.

Writing design to file carry_lookahead_adder.ncd.


PAR done.