Project Navigator Auto-Make Log File ------------------------------------- Started process "Check Syntax". ========================================================================= * HDL Compilation * ========================================================================= WARNING:HDLParsers:3458 - Because of erroneous VHDL in VHDL file z:\camurati\esercitazione_1/es_1.vhd, automatic determination of correct order of compilation of files in project file es_1_vhdl.prj is not possible. Please compile your vhdl file(s) individually to find and fix the error(s) in your vhdl file(s). Defaulting to compilation in the order vhdl file names appear in the project file. Compiling vhdl file z:\camurati\esercitazione_1/es_1.vhd in Library work. ERROR:HDLParsers:164 - z:\camurati\esercitazione_1/es_1.vhd Line 12. parse error, unexpected CLOSEPAR, expecting IDENTIFIER WARNING:HDLParsers:3465 - Library as no units. Did not save reference file xst/work/hdllib.ref for it. ERROR: XST failed Process "Check Syntax" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Check Syntax". ========================================================================= * HDL Compilation * ========================================================================= WARNING:HDLParsers:3458 - Because of erroneous VHDL in VHDL file z:\camurati\esercitazione_1/es_1.vhd, automatic determination of correct order of compilation of files in project file es_1_vhdl.prj is not possible. Please compile your vhdl file(s) individually to find and fix the error(s) in your vhdl file(s). Defaulting to compilation in the order vhdl file names appear in the project file. Compiling vhdl file z:\camurati\esercitazione_1/es_1.vhd in Library work. ERROR:HDLParsers:164 - z:\camurati\esercitazione_1/es_1.vhd Line 12. parse error, unexpected CLOSEPAR, expecting IDENTIFIER WARNING:HDLParsers:3465 - Library as no units. Did not save reference file xst/work/hdllib.ref for it. ERROR: XST failed Process "Check Syntax" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Check Syntax". ========================================================================= * HDL Compilation * ========================================================================= WARNING:HDLParsers:3458 - Because of erroneous VHDL in VHDL file z:\camurati\esercitazione_1/es_1.vhd, automatic determination of correct order of compilation of files in project file es_1_vhdl.prj is not possible. Please compile your vhdl file(s) individually to find and fix the error(s) in your vhdl file(s). Defaulting to compilation in the order vhdl file names appear in the project file. Compiling vhdl file z:\camurati\esercitazione_1/es_1.vhd in Library work. ERROR:HDLParsers:3402 - z:\camurati\esercitazione_1/es_1.vhd Line 25. Read symbol =, expecting <= or := ERROR:HDLParsers:3402 - z:\camurati\esercitazione_1/es_1.vhd Line 26. Read symbol =, expecting <= or := ERROR:HDLParsers:164 - z:\camurati\esercitazione_1/es_1.vhd Line 30. parse error, unexpected PROCESS, expecting IF ERROR:HDLParsers:164 - z:\camurati\esercitazione_1/es_1.vhd Line 35. parse error, unexpected IDENTIFIER, expecting IF ERROR: XST failed Process "Check Syntax" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Check Syntax". ========================================================================= * HDL Compilation * ========================================================================= WARNING:HDLParsers:3458 - Because of erroneous VHDL in VHDL file z:\camurati\esercitazione_1/es_1.vhd, automatic determination of correct order of compilation of files in project file es_1_vhdl.prj is not possible. Please compile your vhdl file(s) individually to find and fix the error(s) in your vhdl file(s). Defaulting to compilation in the order vhdl file names appear in the project file. Compiling vhdl file z:\camurati\esercitazione_1/es_1.vhd in Library work. ERROR:HDLParsers:800 - z:\camurati\esercitazione_1/es_1.vhd Line 25. Type of sum is incompatible with type of 0. ERROR:HDLParsers:800 - z:\camurati\esercitazione_1/es_1.vhd Line 26. Type of carry_out is incompatible with type of 0. ERROR:HDLParsers:164 - z:\camurati\esercitazione_1/es_1.vhd Line 30. parse error, unexpected PROCESS, expecting IF ERROR:HDLParsers:164 - z:\camurati\esercitazione_1/es_1.vhd Line 35. parse error, unexpected IDENTIFIER, expecting IF ERROR: XST failed Process "Check Syntax" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Check Syntax". ========================================================================= * HDL Compilation * ========================================================================= WARNING:HDLParsers:3458 - Because of erroneous VHDL in VHDL file z:\camurati\esercitazione_1/es_1.vhd, automatic determination of correct order of compilation of files in project file es_1_vhdl.prj is not possible. Please compile your vhdl file(s) individually to find and fix the error(s) in your vhdl file(s). Defaulting to compilation in the order vhdl file names appear in the project file. Compiling vhdl file z:\camurati\esercitazione_1/es_1.vhd in Library work. ERROR:HDLParsers:164 - z:\camurati\esercitazione_1/es_1.vhd Line 30. parse error, unexpected PROCESS, expecting IF ERROR:HDLParsers:164 - z:\camurati\esercitazione_1/es_1.vhd Line 35. parse error, unexpected IDENTIFIER, expecting IF ERROR: XST failed Process "Check Syntax" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Check Syntax". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file z:/camurati/esercitazione_1/es_1.vhd in Library work. Entity (Architecture ) compiled. Completed process "Check Syntax". Project Navigator Auto-Make Log File ------------------------------------- Started process "Check Syntax". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file z:/camurati/esercitazione_1/es_1.vhd in Library work. Architecture behavioral of Entity es_1 is up to date. Completed process "Check Syntax". Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file z:/camurati/esercitazione_1/es_1.vhd in Library work. Architecture behavioral of Entity es_1 is up to date. ========================================================================= * HDL Analysis * ========================================================================= Analyzing Entity (Architecture ). WARNING:Xst:819 - z:/camurati/esercitazione_1/es_1.vhd line 22: The following signals are missing in the process sensitivity list: ce. Entity analyzed. Unit generated. ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is z:/camurati/esercitazione_1/es_1.vhd. Found 1-bit xor2 for signal <$n0001> created at line 28. Found 1-bit xor2 for signal <$n0005> created at line 29. Unit synthesized. ========================================================================= * Advanced HDL Synthesis * ========================================================================= Advanced RAM inference ... Advanced multiplier inference ... Advanced Registered AddSub inference ... Dynamic shift register inference ... ========================================================================= HDL Synthesis Report Macro Statistics # Xors : 2 1-bit xor2 : 2 ========================================================================= ========================================================================= * Low Level Synthesis * ========================================================================= Optimizing unit ... Loading device for application Xst from file '3s200.nph' in environment C:/Program Files/Xilinx. Mapping all equations... Building and optimizing final netlist ... Found area constraint ratio of 100 (+ 5) on block es_1, actual ratio is 0. ========================================================================= * Final Report * ========================================================================= Device utilization summary: --------------------------- Selected Device : 3s200ft256-4 Number of Slices: 1 out of 1920 0% Number of 4 input LUTs: 2 out of 3840 0% Number of bonded IOBs: 6 out of 173 3% ========================================================================= TIMING REPORT Clock Information: ------------------ No clock signals found in this design Timing Summary: --------------- Speed Grade: -4 Minimum period: No path found Minimum input arrival time before clock: No path found Maximum output required time after clock: No path found Maximum combinational path delay: 8.061ns ========================================================================= Completed process "Synthesize". Started process "Translate". Command Line: ngdbuild -intstyle ise -dd z:\camurati\esercitazione_1/_ngo -i -p xc3s200-ft256-4 es_1.ngc es_1.ngd Reading NGO file "z:/camurati/esercitazione_1/es_1.ngc" ... Reading component libraries for design expansion... Checking timing specifications ... Checking expanded design ... NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0 Total memory usage is 38140 kilobytes Writing NGD file "es_1.ngd" ... Writing NGDBUILD log file "es_1.bld"... NGDBUILD done. Completed process "Translate". Project Navigator Auto-Make Log File ------------------------------------- Started process "Translate". Command Line: ngdbuild -intstyle ise -dd z:\camurati\esercitazione_1/_ngo -uc es_1.ucf -p xc3s200-ft256-4 es_1.ngc es_1.ngd Reading NGO file "z:/camurati/esercitazione_1/es_1.ngc" ... Reading component libraries for design expansion... Annotating constraints to design from file "es_1.ucf" ... Checking timing specifications ... Checking expanded design ... NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0 Total memory usage is 39164 kilobytes Writing NGD file "es_1.ngd" ... Writing NGDBUILD log file "es_1.bld"... NGDBUILD done. Completed process "Translate". Started process "Map". Using target part "3s200ft256-4". Removing unused or disabled logic... Running cover... Running directed packing... Running delay-based LUT packing... Running related packing... Design Summary: Number of errors: 0 Number of warnings: 0 Logic Utilization: Number of 4 input LUTs: 2 out of 3,840 1% Logic Distribution: Number of occupied Slices: 1 out of 1,920 1% Number of Slices containing only related logic: 1 out of 1 100% Number of Slices containing unrelated logic: 0 out of 1 0% *See NOTES below for an explanation of the effects of unrelated logic Total Number of 4 input LUTs: 2 out of 3,840 1% Number of bonded IOBs: 6 out of 173 3% Total equivalent gate count for design: 12 Additional JTAG gate count for IOBs: 288 Peak Memory Usage: 66 MB NOTES: Related logic is defined as being logic that shares connectivity - e.g. two LUTs are "related" if they share common inputs. When assembling slices, Map gives priority to combine logic that is related. Doing so results in the best timing performance. Unrelated logic shares no connectivity. Map will only begin packing unrelated logic into a slice once 99% of the slices are occupied through related logic packing. Note that once logic distribution reaches the 99% level through related logic packing, this does not mean the device is completely utilized. Unrelated logic packing will then begin, continuing until all usable LUTs and FFs are occupied. Depending on your timing budget, increased levels of unrelated logic packing may adversely affect the overall timing performance of your design. Mapping completed. See MAP report file "es_1_map.mrp" for details. Completed process "Map". Mapping Module es_1 . . . MAP command line: map -intstyle ise -p xc3s200-ft256-4 -cm area -pr b -k 4 -c 100 -tx off -o es_1_map.ncd es_1.ngd es_1.pcf Mapping Module es_1: DONE Started process "Place & Route". Constraints file: es_1.pcf Loading device database for application Par from file "es_1_map.ncd". "es_1" is an NCD, version 2.38, device xc3s200, package ft256, speed -4 Loading device for application Par from file '3s200.nph' in environment C:/Program Files/Xilinx. Device speed data version: PRODUCTION 1.32 2004-06-25. Resolving physical constraints. Finished resolving physical constraints. Device utilization summary: Number of External IOBs 6 out of 173 3% Number of LOCed External IOBs 6 out of 6 100% Number of Slices 1 out of 1920 1% Overall effort level (-ol): Standard (set by user) Placer effort level (-pl): Standard (set by user) Placer cost table entry (-t): 1 Router effort level (-rl): Standard (set by user) Phase 1.1 Phase 1.1 (Checksum:98968d) REAL time: 0 secs Phase 3.8 . Phase 3.8 (Checksum:98a273) REAL time: 0 secs Phase 4.5 Phase 4.5 (Checksum:26259fc) REAL time: 0 secs Phase 5.18 Phase 5.18 (Checksum:2faf07b) REAL time: 0 secs Writing design to file es_1.ncd. Total REAL time to Placer completion: 0 secs Total CPU time to Placer completion: 0 secs Phase 1: 10 unrouted; REAL time: 2 secs Phase 2: 10 unrouted; REAL time: 2 secs Phase 3: 0 unrouted; REAL time: 2 secs Phase 4: 0 unrouted; REAL time: 2 secs Total REAL time to Router completion: 2 secs Total CPU time to Router completion: 0 secs Generating "par" statistics. Generating Pad Report. All signals are completely routed. Total REAL time to PAR completion: 6 secs Total CPU time to PAR completion: 1 secs Peak Memory Usage: 55 MB Placement: Completed - No errors found. Routing: Completed - No errors found. Writing design to file es_1.ncd. PAR done. Completed process "Place & Route". Started process "Generate Post-Place & Route Static Timing". Analysis completed Fri Mar 02 09:26:27 2007 -------------------------------------------------------------------------------- Generating Report ... Completed process "Generate Post-Place & Route Static Timing". Place & Route Module es_1 . . . PAR command line: par -w -intstyle ise -ol std -t 1 es_1_map.ncd es_1.ncd es_1.pcf PAR completed successfully Started process "Generate Programming File". Completed process "Generate Programming File". Project Navigator Auto-Make Log File ------------------------------------- Project Navigator Auto-Make Log File ------------------------------------- Launching Application for process "Generate Expected Simulation Results". Reading c:/program files/Modeltech_xe_starter/win32xoem/../tcl/vsim/pref.tcl # 5.8c # do test_fa.ado listening on address 127.0.0.1 port 1200 # resume # Model Technology ModelSim XE II vcom 5.8c Compiler 2004.03 Mar 26 2004 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity es_1 # -- Compiling architecture behavioral of es_1 # Model Technology ModelSim XE II vcom 5.8c Compiler 2004.03 Mar 26 2004 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity test_fa # -- Compiling architecture testbench_arch of test_fa # -- Loading entity es_1 # -- Compiling configuration es_1_cfg # -- Loading entity test_fa # -- Loading architecture testbench_arch of test_fa # vsim -lib work -t 1ps test_fa # Loading c:\program files\Modeltech_xe_starter\win32xoem/../std.standard # Loading c:\program files\Modeltech_xe_starter\win32xoem/../ieee.std_logic_1164(body) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../ieee.std_logic_arith(body) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../ieee.std_logic_unsigned(body) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../std.textio(body) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../ieee.std_logic_textio(body) # Loading work.test_fa(testbench_arch) # Loading work.es_1(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 1950 ns Iteration: 0 Process: /test_fa/line__96 File: test_fa.ant # Break at test_fa.ant line 129 # Stopped at test_fa.ant line 129 Project Navigator Auto-Make Log File ------------------------------------- Started process "Generate Post-Place & Route Simulation Model". Completed process "Generate Post-Place & Route Simulation Model". Compiling vhdl file z:/camurati/esercitazione_1/es_1.vhd in Library work. Entity (Architecture ) compiled. Project Navigator Auto-Make Log File ------------------------------------- Started process "Translate". Command Line: ngdbuild -intstyle ise -dd z:\camurati\esercitazione_1/_ngo -uc es_1.ucf -p xc3s200-ft256-4 es_1.ngc es_1.ngd Reading NGO file "z:/camurati/esercitazione_1/es_1.ngc" ... Reading component libraries for design expansion... Annotating constraints to design from file "es_1.ucf" ... Checking timing specifications ... Checking expanded design ... NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0 Total memory usage is 39164 kilobytes Writing NGD file "es_1.ngd" ... Writing NGDBUILD log file "es_1.bld"... NGDBUILD done. Completed process "Translate". Started process "Map". Using target part "3s200ft256-4". Removing unused or disabled logic... Running cover... Running directed packing... Running delay-based LUT packing... Running related packing... Design Summary: Number of errors: 0 Number of warnings: 0 Logic Utilization: Number of 4 input LUTs: 2 out of 3,840 1% Logic Distribution: Number of occupied Slices: 1 out of 1,920 1% Number of Slices containing only related logic: 1 out of 1 100% Number of Slices containing unrelated logic: 0 out of 1 0% *See NOTES below for an explanation of the effects of unrelated logic Total Number of 4 input LUTs: 2 out of 3,840 1% Number of bonded IOBs: 6 out of 173 3% Total equivalent gate count for design: 12 Additional JTAG gate count for IOBs: 288 Peak Memory Usage: 66 MB NOTES: Related logic is defined as being logic that shares connectivity - e.g. two LUTs are "related" if they share common inputs. When assembling slices, Map gives priority to combine logic that is related. Doing so results in the best timing performance. Unrelated logic shares no connectivity. Map will only begin packing unrelated logic into a slice once 99% of the slices are occupied through related logic packing. Note that once logic distribution reaches the 99% level through related logic packing, this does not mean the device is completely utilized. Unrelated logic packing will then begin, continuing until all usable LUTs and FFs are occupied. Depending on your timing budget, increased levels of unrelated logic packing may adversely affect the overall timing performance of your design. Mapping completed. See MAP report file "es_1_map.mrp" for details. Completed process "Map". Mapping Module es_1 . . . MAP command line: map -intstyle ise -p xc3s200-ft256-4 -cm area -pr b -k 4 -c 100 -tx off -o es_1_map.ncd es_1.ngd es_1.pcf Mapping Module es_1: DONE Started process "Place & Route". Constraints file: es_1.pcf Loading device database for application Par from file "es_1_map.ncd". "es_1" is an NCD, version 2.38, device xc3s200, package ft256, speed -4 Loading device for application Par from file '3s200.nph' in environment C:/Program Files/Xilinx. Device speed data version: PRODUCTION 1.32 2004-06-25. Resolving physical constraints. Finished resolving physical constraints. Device utilization summary: Number of External IOBs 6 out of 173 3% Number of LOCed External IOBs 5 out of 6 83% Number of Slices 1 out of 1920 1% Overall effort level (-ol): Standard (set by user) Placer effort level (-pl): Standard (set by user) Placer cost table entry (-t): 1 Router effort level (-rl): Standard (set by user) Phase 1.1 Phase 1.1 (Checksum:98968d) REAL time: 0 secs Phase 3.3 Phase 3.3 (Checksum:1c9c37d) REAL time: 0 secs Phase 4.5 Phase 4.5 (Checksum:26259fc) REAL time: 0 secs Phase 5.8 . Phase 5.8 (Checksum:98a2cd) REAL time: 0 secs Phase 6.5 Phase 6.5 (Checksum:39386fa) REAL time: 0 secs Phase 7.18 Phase 7.18 (Checksum:42c1d79) REAL time: 0 secs Writing design to file es_1.ncd. Total REAL time to Placer completion: 0 secs Total CPU time to Placer completion: 0 secs Phase 1: 10 unrouted; REAL time: 0 secs Phase 2: 10 unrouted; REAL time: 0 secs Phase 3: 4 unrouted; REAL time: 0 secs Phase 4: 0 unrouted; REAL time: 0 secs Total REAL time to Router completion: 0 secs Total CPU time to Router completion: 0 secs Generating "par" statistics. Generating Pad Report. All signals are completely routed. Total REAL time to PAR completion: 6 secs Total CPU time to PAR completion: 1 secs Peak Memory Usage: 56 MB Placement: Completed - No errors found. Routing: Completed - No errors found. Writing design to file es_1.ncd. PAR done. Completed process "Place & Route". Started process "Generate Post-Place & Route Static Timing". Analysis completed Fri Mar 02 09:42:12 2007 -------------------------------------------------------------------------------- Generating Report ... Completed process "Generate Post-Place & Route Static Timing". Place & Route Module es_1 . . . PAR command line: par -w -intstyle ise -ol std -t 1 es_1_map.ncd es_1.ncd es_1.pcf PAR completed successfully Started process "Generate Programming File". Completed process "Generate Programming File". Project Navigator Auto-Make Log File ------------------------------------- Started process "Translate". Command Line: ngdbuild -intstyle ise -dd z:\camurati\esercitazione_1/_ngo -uc es_1.ucf -p xc3s200-ft256-4 es_1.ngc es_1.ngd Reading NGO file "z:/camurati/esercitazione_1/es_1.ngc" ... Reading component libraries for design expansion... Annotating constraints to design from file "es_1.ucf" ... Checking timing specifications ... Checking expanded design ... NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0 Total memory usage is 39164 kilobytes Writing NGD file "es_1.ngd" ... Writing NGDBUILD log file "es_1.bld"... NGDBUILD done. Completed process "Translate". Started process "Map". Using target part "3s200ft256-4". Removing unused or disabled logic... Running cover... Running directed packing... Running delay-based LUT packing... Running related packing... Design Summary: Number of errors: 0 Number of warnings: 0 Logic Utilization: Number of 4 input LUTs: 2 out of 3,840 1% Logic Distribution: Number of occupied Slices: 1 out of 1,920 1% Number of Slices containing only related logic: 1 out of 1 100% Number of Slices containing unrelated logic: 0 out of 1 0% *See NOTES below for an explanation of the effects of unrelated logic Total Number of 4 input LUTs: 2 out of 3,840 1% Number of bonded IOBs: 6 out of 173 3% Total equivalent gate count for design: 12 Additional JTAG gate count for IOBs: 288 Peak Memory Usage: 66 MB NOTES: Related logic is defined as being logic that shares connectivity - e.g. two LUTs are "related" if they share common inputs. When assembling slices, Map gives priority to combine logic that is related. Doing so results in the best timing performance. Unrelated logic shares no connectivity. Map will only begin packing unrelated logic into a slice once 99% of the slices are occupied through related logic packing. Note that once logic distribution reaches the 99% level through related logic packing, this does not mean the device is completely utilized. Unrelated logic packing will then begin, continuing until all usable LUTs and FFs are occupied. Depending on your timing budget, increased levels of unrelated logic packing may adversely affect the overall timing performance of your design. Mapping completed. See MAP report file "es_1_map.mrp" for details. Completed process "Map". Mapping Module es_1 . . . MAP command line: map -intstyle ise -p xc3s200-ft256-4 -cm area -pr b -k 4 -c 100 -tx off -o es_1_map.ncd es_1.ngd es_1.pcf Mapping Module es_1: DONE Started process "Place & Route". Constraints file: es_1.pcf Loading device database for application Par from file "es_1_map.ncd". "es_1" is an NCD, version 2.38, device xc3s200, package ft256, speed -4 Loading device for application Par from file '3s200.nph' in environment C:/Program Files/Xilinx. Device speed data version: PRODUCTION 1.32 2004-06-25. Resolving physical constraints. Finished resolving physical constraints. Device utilization summary: Number of External IOBs 6 out of 173 3% Number of LOCed External IOBs 5 out of 6 83% Number of Slices 1 out of 1920 1% Overall effort level (-ol): Standard (set by user) Placer effort level (-pl): Standard (set by user) Placer cost table entry (-t): 1 Router effort level (-rl): Standard (set by user) Phase 1.1 Phase 1.1 (Checksum:98968d) REAL time: 0 secs Phase 3.3 Phase 3.3 (Checksum:1c9c37d) REAL time: 0 secs Phase 4.5 Phase 4.5 (Checksum:26259fc) REAL time: 0 secs Phase 5.8 . Phase 5.8 (Checksum:98a2cd) REAL time: 0 secs Phase 6.5 Phase 6.5 (Checksum:39386fa) REAL time: 0 secs Phase 7.18 Phase 7.18 (Checksum:42c1d79) REAL time: 0 secs Writing design to file es_1.ncd. Total REAL time to Placer completion: 0 secs Total CPU time to Placer completion: 0 secs Phase 1: 10 unrouted; REAL time: 0 secs Phase 2: 10 unrouted; REAL time: 0 secs Phase 3: 4 unrouted; REAL time: 0 secs Phase 4: 0 unrouted; REAL time: 0 secs Total REAL time to Router completion: 0 secs Total CPU time to Router completion: 0 secs Generating "par" statistics. Generating Pad Report. All signals are completely routed. Total REAL time to PAR completion: 5 secs Total CPU time to PAR completion: 1 secs Peak Memory Usage: 56 MB Placement: Completed - No errors found. Routing: Completed - No errors found. Writing design to file es_1.ncd. PAR done. Completed process "Place & Route". Started process "Generate Post-Place & Route Static Timing". Analysis completed Fri Mar 02 09:44:08 2007 -------------------------------------------------------------------------------- Generating Report ... Completed process "Generate Post-Place & Route Static Timing". Place & Route Module es_1 . . . PAR command line: par -w -intstyle ise -ol std -t 1 es_1_map.ncd es_1.ncd es_1.pcf PAR completed successfully Started process "Generate Programming File". Completed process "Generate Programming File". Project Navigator Auto-Make Log File ------------------------------------- Started process "Translate". Command Line: ngdbuild -intstyle ise -dd z:\camurati\esercitazione_1/_ngo -uc es_1.ucf -p xc3s200-ft256-4 es_1.ngc es_1.ngd Reading NGO file "z:/camurati/esercitazione_1/es_1.ngc" ... Reading component libraries for design expansion... Annotating constraints to design from file "es_1.ucf" ... Checking timing specifications ... Checking expanded design ... NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0 Total memory usage is 39164 kilobytes Writing NGD file "es_1.ngd" ... Writing NGDBUILD log file "es_1.bld"... NGDBUILD done. Completed process "Translate". Started process "Map". Using target part "3s200ft256-4". Removing unused or disabled logic... Running cover... Running directed packing... Running delay-based LUT packing... Running related packing... Design Summary: Number of errors: 0 Number of warnings: 0 Logic Utilization: Number of 4 input LUTs: 2 out of 3,840 1% Logic Distribution: Number of occupied Slices: 1 out of 1,920 1% Number of Slices containing only related logic: 1 out of 1 100% Number of Slices containing unrelated logic: 0 out of 1 0% *See NOTES below for an explanation of the effects of unrelated logic Total Number of 4 input LUTs: 2 out of 3,840 1% Number of bonded IOBs: 6 out of 173 3% Total equivalent gate count for design: 12 Additional JTAG gate count for IOBs: 288 Peak Memory Usage: 66 MB NOTES: Related logic is defined as being logic that shares connectivity - e.g. two LUTs are "related" if they share common inputs. When assembling slices, Map gives priority to combine logic that is related. Doing so results in the best timing performance. Unrelated logic shares no connectivity. Map will only begin packing unrelated logic into a slice once 99% of the slices are occupied through related logic packing. Note that once logic distribution reaches the 99% level through related logic packing, this does not mean the device is completely utilized. Unrelated logic packing will then begin, continuing until all usable LUTs and FFs are occupied. Depending on your timing budget, increased levels of unrelated logic packing may adversely affect the overall timing performance of your design. Mapping completed. See MAP report file "es_1_map.mrp" for details. Completed process "Map". Mapping Module es_1 . . . MAP command line: map -intstyle ise -p xc3s200-ft256-4 -cm area -pr b -k 4 -c 100 -tx off -o es_1_map.ncd es_1.ngd es_1.pcf Mapping Module es_1: DONE Started process "Place & Route". Constraints file: es_1.pcf Loading device database for application Par from file "es_1_map.ncd". "es_1" is an NCD, version 2.38, device xc3s200, package ft256, speed -4 Loading device for application Par from file '3s200.nph' in environment C:/Program Files/Xilinx. Device speed data version: PRODUCTION 1.32 2004-06-25. Resolving physical constraints. Finished resolving physical constraints. Device utilization summary: Number of External IOBs 6 out of 173 3% Number of LOCed External IOBs 6 out of 6 100% Number of Slices 1 out of 1920 1% Overall effort level (-ol): Standard (set by user) Placer effort level (-pl): Standard (set by user) Placer cost table entry (-t): 1 Router effort level (-rl): Standard (set by user) Phase 1.1 Phase 1.1 (Checksum:98968d) REAL time: 0 secs Phase 3.8 . Phase 3.8 (Checksum:98a273) REAL time: 0 secs Phase 4.5 Phase 4.5 (Checksum:26259fc) REAL time: 0 secs Phase 5.18 Phase 5.18 (Checksum:2faf07b) REAL time: 0 secs Writing design to file es_1.ncd. Total REAL time to Placer completion: 0 secs Total CPU time to Placer completion: 0 secs Phase 1: 10 unrouted; REAL time: 0 secs Phase 2: 10 unrouted; REAL time: 0 secs Phase 3: 0 unrouted; REAL time: 0 secs Phase 4: 0 unrouted; REAL time: 0 secs Total REAL time to Router completion: 0 secs Total CPU time to Router completion: 0 secs Generating "par" statistics. Generating Pad Report. All signals are completely routed. Total REAL time to PAR completion: 5 secs Total CPU time to PAR completion: 1 secs Peak Memory Usage: 55 MB Placement: Completed - No errors found. Routing: Completed - No errors found. Writing design to file es_1.ncd. PAR done. Completed process "Place & Route". Started process "Generate Post-Place & Route Static Timing". Analysis completed Fri Mar 02 09:46:45 2007 -------------------------------------------------------------------------------- Generating Report ... Completed process "Generate Post-Place & Route Static Timing". Place & Route Module es_1 . . . PAR command line: par -w -intstyle ise -ol std -t 1 es_1_map.ncd es_1.ncd es_1.pcf PAR completed successfully Started process "Generate Programming File". Completed process "Generate Programming File". Project Navigator Auto-Make Log File ------------------------------------- Started process "Create Schematic Symbol". Compiling vhdl file z:/camurati/esercitazione_1/es_1.vhd in Library work. Entity (Architecture ) compiled. tdtfi(vhdl) completed successfully. Release 6.3i - spl2sym G.35 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. Completed process "Create Schematic Symbol". Project Navigator Auto-Make Log File ------------------------------------- Started process "View VHDL Functional Model". Release 6.3i - sch2vhdl G.35 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. DRC Check completed: No Error found. Vhdl netlist file generated. Completed process "View VHDL Functional Model". Project Navigator Auto-Make Log File ------------------------------------- Launching Application for process "Generate Expected Simulation Results". Reading c:/program files/Modeltech_xe_starter/win32xoem/../tcl/vsim/pref.tcl # 5.8c # do rca_tester.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.8c Compiler 2004.03 Mar 26 2004 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity es_1 # -- Compiling architecture behavioral of es_1 # Model Technology ModelSim XE II vcom 5.8c Compiler 2004.03 Mar 26 2004 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package numeric_std # -- Loading package vital_timing # -- Loading package vcomponents # -- Compiling entity ripple_carry_adder # -- Compiling architecture behavioral of ripple_carry_adder # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading entity es_1 # Model Technology ModelSim XE II vcom 5.8c Compiler 2004.03 Mar 26 2004 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package numeric_std # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity rca_tester # -- Compiling architecture testbench_arch of rca_tester # -- Loading package vital_timing # -- Loading package vcomponents # -- Loading entity ripple_carry_adder # -- Compiling configuration ripple_carry_adder_cfg # -- Loading entity rca_tester # -- Loading architecture testbench_arch of rca_tester # vsim -lib work -t 1ps rca_tester # Loading c:\program files\Modeltech_xe_starter\win32xoem/../std.standard # Loading c:\program files\Modeltech_xe_starter\win32xoem/../ieee.std_logic_1164(body) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../ieee.numeric_std(body) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../std.textio(body) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../ieee.std_logic_textio(body) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../ieee.vital_timing(body) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../xilinx/vhdl/unisim.vcomponents # Loading work.rca_tester(testbench_arch) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../ieee.std_logic_arith(body) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../ieee.std_logic_unsigned(body) # Loading work.ripple_carry_adder(behavioral) # Loading work.es_1(behavioral) # ** Failure: Success! Simulation for annotation completed # Time: 1350 ns Iteration: 0 Process: /rca_tester/line__95 File: rca_tester.ant # Break at rca_tester.ant line 139 # Stopped at rca_tester.ant line 139 Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file z:/camurati/esercitazione_1/es_1.vhd in Library work. Architecture behavioral of Entity es_1 is up to date. Compiling vhdl file z:/camurati/esercitazione_1/ripple_carry_adder.vhf in Library work. Architecture behavioral of Entity ripple_carry_adder is up to date. ========================================================================= * HDL Analysis * ========================================================================= Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). WARNING:Xst:819 - z:/camurati/esercitazione_1/es_1.vhd line 22: The following signals are missing in the process sensitivity list: ce. Entity analyzed. Unit generated. ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is z:/camurati/esercitazione_1/es_1.vhd. Found 1-bit xor2 for signal <$n0001> created at line 28. Found 1-bit xor2 for signal <$n0005> created at line 29. Unit synthesized. Synthesizing Unit . Related source file is z:/camurati/esercitazione_1/ripple_carry_adder.vhf. Unit synthesized. ========================================================================= * Advanced HDL Synthesis * ========================================================================= Advanced RAM inference ... Advanced multiplier inference ... Advanced Registered AddSub inference ... Dynamic shift register inference ... ========================================================================= HDL Synthesis Report Macro Statistics # Xors : 8 1-bit xor2 : 8 ========================================================================= ========================================================================= * Low Level Synthesis * ========================================================================= Optimizing unit ... Loading device for application Xst from file '3s200.nph' in environment C:/Program Files/Xilinx. Mapping all equations... Building and optimizing final netlist ... Found area constraint ratio of 100 (+ 5) on block ripple_carry_adder, actual ratio is 0. ========================================================================= * Final Report * ========================================================================= Device utilization summary: --------------------------- Selected Device : 3s200ft256-4 Number of Slices: 6 out of 1920 0% Number of 4 input LUTs: 11 out of 3840 0% Number of bonded IOBs: 15 out of 173 8% ========================================================================= TIMING REPORT Clock Information: ------------------ No clock signals found in this design Timing Summary: --------------- Speed Grade: -4 Minimum period: No path found Minimum input arrival time before clock: No path found Maximum output required time after clock: No path found Maximum combinational path delay: 11.048ns ========================================================================= Completed process "Synthesize". Started process "Translate". Command Line: ngdbuild -intstyle ise -dd z:\camurati\esercitazione_1/_ngo -i -p xc3s200-ft256-4 ripple_carry_adder.ngc ripple_carry_adder.ngd Reading NGO file "z:/camurati/esercitazione_1/ripple_carry_adder.ngc" ... Reading component libraries for design expansion... Checking timing specifications ... Checking expanded design ... NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0 Total memory usage is 38140 kilobytes Writing NGD file "ripple_carry_adder.ngd" ... Writing NGDBUILD log file "ripple_carry_adder.bld"... NGDBUILD done. Completed process "Translate". Started process "Map". Using target part "3s200ft256-4". Removing unused or disabled logic... Running cover... Running directed packing... Running delay-based LUT packing... Running related packing... Design Summary: Number of errors: 0 Number of warnings: 0 Logic Utilization: Number of 4 input LUTs: 11 out of 3,840 1% Logic Distribution: Number of occupied Slices: 6 out of 1,920 1% Number of Slices containing only related logic: 6 out of 6 100% Number of Slices containing unrelated logic: 0 out of 6 0% *See NOTES below for an explanation of the effects of unrelated logic Total Number of 4 input LUTs: 11 out of 3,840 1% Number of bonded IOBs: 15 out of 173 8% Total equivalent gate count for design: 66 Additional JTAG gate count for IOBs: 720 Peak Memory Usage: 66 MB NOTES: Related logic is defined as being logic that shares connectivity - e.g. two LUTs are "related" if they share common inputs. When assembling slices, Map gives priority to combine logic that is related. Doing so results in the best timing performance. Unrelated logic shares no connectivity. Map will only begin packing unrelated logic into a slice once 99% of the slices are occupied through related logic packing. Note that once logic distribution reaches the 99% level through related logic packing, this does not mean the device is completely utilized. Unrelated logic packing will then begin, continuing until all usable LUTs and FFs are occupied. Depending on your timing budget, increased levels of unrelated logic packing may adversely affect the overall timing performance of your design. Mapping completed. See MAP report file "ripple_carry_adder_map.mrp" for details. Completed process "Map". Mapping Module ripple_carry_adder . . . MAP command line: map -intstyle ise -p xc3s200-ft256-4 -cm area -pr b -k 4 -c 100 -tx off -o ripple_carry_adder_map.ncd ripple_carry_adder.ngd ripple_carry_adder.pcf Mapping Module ripple_carry_adder: DONE Started process "Place & Route". Constraints file: ripple_carry_adder.pcf Loading device database for application Par from file "ripple_carry_adder_map.ncd". "ripple_carry_adder" is an NCD, version 2.38, device xc3s200, package ft256, speed -4 Loading device for application Par from file '3s200.nph' in environment C:/Program Files/Xilinx. Device speed data version: PRODUCTION 1.32 2004-06-25. Resolving physical constraints. Finished resolving physical constraints. Device utilization summary: Number of External IOBs 15 out of 173 8% Number of LOCed External IOBs 0 out of 15 0% Number of Slices 6 out of 1920 1% Overall effort level (-ol): Standard (set by user) Placer effort level (-pl): Standard (set by user) Placer cost table entry (-t): 1 Router effort level (-rl): Standard (set by user) Phase 1.1 Phase 1.1 (Checksum:9896a9) REAL time: 0 secs Phase 3.3 Phase 3.3 (Checksum:1c9c37d) REAL time: 0 secs Phase 4.5 Phase 4.5 (Checksum:26259fc) REAL time: 0 secs Phase 5.8 . Phase 5.8 (Checksum:98acc3) REAL time: 0 secs Phase 6.5 Phase 6.5 (Checksum:39386fa) REAL time: 0 secs Phase 7.18 Phase 7.18 (Checksum:42c1d79) REAL time: 0 secs Writing design to file ripple_carry_adder.ncd. Total REAL time to Placer completion: 0 secs Total CPU time to Placer completion: 0 secs Phase 1: 45 unrouted; REAL time: 0 secs Phase 2: 45 unrouted; REAL time: 0 secs Phase 3: 24 unrouted; REAL time: 0 secs Phase 4: 0 unrouted; REAL time: 0 secs Total REAL time to Router completion: 0 secs Total CPU time to Router completion: 0 secs Generating "par" statistics. Generating Pad Report. All signals are completely routed. Total REAL time to PAR completion: 5 secs Total CPU time to PAR completion: 1 secs Peak Memory Usage: 56 MB Placement: Completed - No errors found. Routing: Completed - No errors found. Writing design to file ripple_carry_adder.ncd. PAR done. Completed process "Place & Route". Started process "Generate Post-Place & Route Static Timing". Analysis completed Fri Mar 02 10:29:23 2007 -------------------------------------------------------------------------------- Generating Report ... Completed process "Generate Post-Place & Route Static Timing". Place & Route Module ripple_carry_adder . . . PAR command line: par -w -intstyle ise -ol std -t 1 ripple_carry_adder_map.ncd ripple_carry_adder.ncd ripple_carry_adder.pcf PAR completed successfully Started process "Generate Post-Place & Route Simulation Model". Completed process "Generate Post-Place & Route Simulation Model". Compiling vhdl file z:/camurati/esercitazione_1/ripple_carry_adder.vhf in Library work. Entity (Architecture ) compiled. Project Navigator Auto-Make Log File ------------------------------------- Started process "Translate". Command Line: ngdbuild -intstyle ise -dd z:\camurati\esercitazione_1/_ngo -uc ripple_carry_adder.ucf -p xc3s200-ft256-4 ripple_carry_adder.ngc ripple_carry_adder.ngd Reading NGO file "z:/camurati/esercitazione_1/ripple_carry_adder.ngc" ... Reading component libraries for design expansion... Annotating constraints to design from file "ripple_carry_adder.ucf" ... Checking timing specifications ... Checking expanded design ... NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0 Total memory usage is 39164 kilobytes Writing NGD file "ripple_carry_adder.ngd" ... Writing NGDBUILD log file "ripple_carry_adder.bld"... NGDBUILD done. Completed process "Translate". Started process "Map". Using target part "3s200ft256-4". Removing unused or disabled logic... Running cover... Running directed packing... Running delay-based LUT packing... Running related packing... Design Summary: Number of errors: 0 Number of warnings: 0 Logic Utilization: Number of 4 input LUTs: 11 out of 3,840 1% Logic Distribution: Number of occupied Slices: 6 out of 1,920 1% Number of Slices containing only related logic: 6 out of 6 100% Number of Slices containing unrelated logic: 0 out of 6 0% *See NOTES below for an explanation of the effects of unrelated logic Total Number of 4 input LUTs: 11 out of 3,840 1% Number of bonded IOBs: 15 out of 173 8% Total equivalent gate count for design: 66 Additional JTAG gate count for IOBs: 720 Peak Memory Usage: 66 MB NOTES: Related logic is defined as being logic that shares connectivity - e.g. two LUTs are "related" if they share common inputs. When assembling slices, Map gives priority to combine logic that is related. Doing so results in the best timing performance. Unrelated logic shares no connectivity. Map will only begin packing unrelated logic into a slice once 99% of the slices are occupied through related logic packing. Note that once logic distribution reaches the 99% level through related logic packing, this does not mean the device is completely utilized. Unrelated logic packing will then begin, continuing until all usable LUTs and FFs are occupied. Depending on your timing budget, increased levels of unrelated logic packing may adversely affect the overall timing performance of your design. Mapping completed. See MAP report file "ripple_carry_adder_map.mrp" for details. Completed process "Map". Mapping Module ripple_carry_adder . . . MAP command line: map -intstyle ise -p xc3s200-ft256-4 -cm area -pr b -k 4 -c 100 -tx off -o ripple_carry_adder_map.ncd ripple_carry_adder.ngd ripple_carry_adder.pcf Mapping Module ripple_carry_adder: DONE Started process "Place & Route". Constraints file: ripple_carry_adder.pcf Loading device database for application Par from file "ripple_carry_adder_map.ncd". "ripple_carry_adder" is an NCD, version 2.38, device xc3s200, package ft256, speed -4 Loading device for application Par from file '3s200.nph' in environment C:/Program Files/Xilinx. Device speed data version: PRODUCTION 1.32 2004-06-25. Resolving physical constraints. Finished resolving physical constraints. Device utilization summary: Number of External IOBs 15 out of 173 8% Number of LOCed External IOBs 15 out of 15 100% Number of Slices 6 out of 1920 1% Overall effort level (-ol): Standard (set by user) Placer effort level (-pl): Standard (set by user) Placer cost table entry (-t): 1 Router effort level (-rl): Standard (set by user) Phase 1.1 Phase 1.1 (Checksum:9896a9) REAL time: 0 secs Phase 3.8 . Phase 3.8 (Checksum:98b245) REAL time: 0 secs Phase 4.5 Phase 4.5 (Checksum:26259fc) REAL time: 0 secs Phase 5.18 Phase 5.18 (Checksum:2faf07b) REAL time: 0 secs Writing design to file ripple_carry_adder.ncd. Total REAL time to Placer completion: 0 secs Total CPU time to Placer completion: 0 secs Phase 1: 45 unrouted; REAL time: 2 secs Phase 2: 45 unrouted; REAL time: 2 secs Phase 3: 23 unrouted; REAL time: 2 secs Phase 4: 0 unrouted; REAL time: 2 secs Total REAL time to Router completion: 2 secs Total CPU time to Router completion: 1 secs Generating "par" statistics. Generating Pad Report. All signals are completely routed. Total REAL time to PAR completion: 5 secs Total CPU time to PAR completion: 1 secs Peak Memory Usage: 55 MB Placement: Completed - No errors found. Routing: Completed - No errors found. Writing design to file ripple_carry_adder.ncd. PAR done. Completed process "Place & Route". Started process "Generate Post-Place & Route Static Timing". Analysis completed Wed Mar 07 10:42:51 2007 -------------------------------------------------------------------------------- Generating Report ... Completed process "Generate Post-Place & Route Static Timing". Place & Route Module ripple_carry_adder . . . PAR command line: par -w -intstyle ise -ol std -t 1 ripple_carry_adder_map.ncd ripple_carry_adder.ncd ripple_carry_adder.pcf PAR completed successfully Started process "Generate Programming File". Completed process "Generate Programming File". Project Navigator Auto-Make Log File ------------------------------------- Started process "Generate Programming File". Completed process "Generate Programming File". Project Navigator Auto-Make Log File ------------------------------------- Started process "Check Syntax". ========================================================================= * HDL Compilation * ========================================================================= WARNING:HDLParsers:3458 - Because of erroneous VHDL in VHDL file z:\camurati\esercitazione_1/Carry_lookahead_logic.vhd, automatic determination of correct order of compilation of files in project file carry_lookahead_logic_vhdl.prj is not possible. Please compile your vhdl file(s) individually to find and fix the error(s) in your vhdl file(s). Defaulting to compilation in the order vhdl file names appear in the project file. Compiling vhdl file z:\camurati\esercitazione_1/Carry_lookahead_logic.vhd in Library work. ERROR:HDLParsers:164 - z:\camurati\esercitazione_1/Carry_lookahead_logic.vhd Line 24. parse error, unexpected IF ERROR:HDLParsers:164 - z:\camurati\esercitazione_1/Carry_lookahead_logic.vhd Line 27. parse error, unexpected ELSE ERROR:HDLParsers:164 - z:\camurati\esercitazione_1/Carry_lookahead_logic.vhd Line 31. parse error, unexpected LE, expecting TICK ERROR: XST failed Process "Check Syntax" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Check Syntax". ========================================================================= * HDL Compilation * ========================================================================= WARNING:HDLParsers:3458 - Because of erroneous VHDL in VHDL file z:\camurati\esercitazione_1/Carry_lookahead_logic.vhd, automatic determination of correct order of compilation of files in project file carry_lookahead_logic_vhdl.prj is not possible. Please compile your vhdl file(s) individually to find and fix the error(s) in your vhdl file(s). Defaulting to compilation in the order vhdl file names appear in the project file. Compiling vhdl file z:\camurati\esercitazione_1/Carry_lookahead_logic.vhd in Library work. ERROR:HDLParsers:164 - z:\camurati\esercitazione_1/Carry_lookahead_logic.vhd Line 28. parse error, unexpected INTEGER_LITERAL, expecting RETURN or IDENTIFIER or RSQBRACK ERROR:HDLParsers:164 - z:\camurati\esercitazione_1/Carry_lookahead_logic.vhd Line 30. parse error, unexpected LE, expecting TICK ERROR:HDLParsers:164 - z:\camurati\esercitazione_1/Carry_lookahead_logic.vhd Line 31. parse error, unexpected LE, expecting TICK ERROR:HDLParsers:164 - z:\camurati\esercitazione_1/Carry_lookahead_logic.vhd Line 33. parse error, unexpected INTEGER_LITERAL, expecting RETURN or IDENTIFIER or RSQBRACK ERROR:HDLParsers:164 - z:\camurati\esercitazione_1/Carry_lookahead_logic.vhd Line 34. parse error, unexpected INTEGER_LITERAL, expecting RETURN or IDENTIFIER or RSQBRACK ERROR:HDLParsers:164 - z:\camurati\esercitazione_1/Carry_lookahead_logic.vhd Line 35. parse error, unexpected INTEGER_LITERAL, expecting RETURN or IDENTIFIER or RSQBRACK ERROR:HDLParsers:164 - z:\camurati\esercitazione_1/Carry_lookahead_logic.vhd Line 36. parse error, unexpected INTEGER_LITERAL, expecting RETURN or IDENTIFIER or RSQBRACK ERROR:HDLParsers:164 - z:\camurati\esercitazione_1/Carry_lookahead_logic.vhd Line 41. parse error, unexpected IDENTIFIER, expecting IF ERROR: XST failed Process "Check Syntax" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Check Syntax". ========================================================================= * HDL Compilation * ========================================================================= WARNING:HDLParsers:3458 - Because of erroneous VHDL in VHDL file z:\camurati\esercitazione_1/Carry_lookahead_logic.vhd, automatic determination of correct order of compilation of files in project file carry_lookahead_logic_vhdl.prj is not possible. Please compile your vhdl file(s) individually to find and fix the error(s) in your vhdl file(s). Defaulting to compilation in the order vhdl file names appear in the project file. Compiling vhdl file z:\camurati\esercitazione_1/Carry_lookahead_logic.vhd in Library work. ERROR:HDLParsers:164 - z:\camurati\esercitazione_1/Carry_lookahead_logic.vhd Line 28. parse error, unexpected INTEGER_LITERAL, expecting RETURN or IDENTIFIER or RSQBRACK ERROR:HDLParsers:164 - z:\camurati\esercitazione_1/Carry_lookahead_logic.vhd Line 30. parse error, unexpected LE, expecting TICK ERROR:HDLParsers:164 - z:\camurati\esercitazione_1/Carry_lookahead_logic.vhd Line 31. parse error, unexpected LE, expecting TICK ERROR:HDLParsers:164 - z:\camurati\esercitazione_1/Carry_lookahead_logic.vhd Line 33. parse error, unexpected INTEGER_LITERAL, expecting RETURN or IDENTIFIER or RSQBRACK ERROR:HDLParsers:164 - z:\camurati\esercitazione_1/Carry_lookahead_logic.vhd Line 34. parse error, unexpected INTEGER_LITERAL, expecting RETURN or IDENTIFIER or RSQBRACK ERROR:HDLParsers:164 - z:\camurati\esercitazione_1/Carry_lookahead_logic.vhd Line 35. parse error, unexpected INTEGER_LITERAL, expecting RETURN or IDENTIFIER or RSQBRACK ERROR:HDLParsers:164 - z:\camurati\esercitazione_1/Carry_lookahead_logic.vhd Line 36. parse error, unexpected INTEGER_LITERAL, expecting RETURN or IDENTIFIER or RSQBRACK ERROR:HDLParsers:164 - z:\camurati\esercitazione_1/Carry_lookahead_logic.vhd Line 41. parse error, unexpected IDENTIFIER, expecting IF ERROR: XST failed Process "Check Syntax" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Check Syntax". ========================================================================= * HDL Compilation * ========================================================================= WARNING:HDLParsers:3458 - Because of erroneous VHDL in VHDL file z:\camurati\esercitazione_1/Carry_lookahead_logic.vhd, automatic determination of correct order of compilation of files in project file carry_lookahead_logic_vhdl.prj is not possible. Please compile your vhdl file(s) individually to find and fix the error(s) in your vhdl file(s). Defaulting to compilation in the order vhdl file names appear in the project file. Compiling vhdl file z:\camurati\esercitazione_1/Carry_lookahead_logic.vhd in Library work. ERROR:HDLParsers:164 - z:\camurati\esercitazione_1/Carry_lookahead_logic.vhd Line 28. parse error, unexpected INTEGER_LITERAL, expecting RETURN or IDENTIFIER or RSQBRACK ERROR:HDLParsers:164 - z:\camurati\esercitazione_1/Carry_lookahead_logic.vhd Line 30. parse error, unexpected LE, expecting TICK ERROR:HDLParsers:164 - z:\camurati\esercitazione_1/Carry_lookahead_logic.vhd Line 31. parse error, unexpected LE, expecting TICK ERROR:HDLParsers:164 - z:\camurati\esercitazione_1/Carry_lookahead_logic.vhd Line 33. parse error, unexpected INTEGER_LITERAL, expecting RETURN or IDENTIFIER or RSQBRACK ERROR:HDLParsers:164 - z:\camurati\esercitazione_1/Carry_lookahead_logic.vhd Line 34. parse error, unexpected INTEGER_LITERAL, expecting RETURN or IDENTIFIER or RSQBRACK ERROR:HDLParsers:164 - z:\camurati\esercitazione_1/Carry_lookahead_logic.vhd Line 35. parse error, unexpected INTEGER_LITERAL, expecting RETURN or IDENTIFIER or RSQBRACK ERROR:HDLParsers:164 - z:\camurati\esercitazione_1/Carry_lookahead_logic.vhd Line 36. parse error, unexpected INTEGER_LITERAL, expecting RETURN or IDENTIFIER or RSQBRACK ERROR:HDLParsers:164 - z:\camurati\esercitazione_1/Carry_lookahead_logic.vhd Line 41. parse error, unexpected IDENTIFIER, expecting IF ERROR: XST failed Process "Check Syntax" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Check Syntax". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file z:/camurati/esercitazione_1/Carry_lookahead_logic.vhd in Library work. ERROR:HDLParsers:164 - z:/camurati/esercitazione_1/Carry_lookahead_logic.vhd Line 28. parse error, unexpected INTEGER_LITERAL, expecting RETURN or IDENTIFIER or RSQBRACK ERROR:HDLParsers:164 - z:/camurati/esercitazione_1/Carry_lookahead_logic.vhd Line 30. parse error, unexpected LE, expecting TICK ERROR:HDLParsers:164 - z:/camurati/esercitazione_1/Carry_lookahead_logic.vhd Line 31. parse error, unexpected LE, expecting TICK ERROR:HDLParsers:164 - z:/camurati/esercitazione_1/Carry_lookahead_logic.vhd Line 33. parse error, unexpected INTEGER_LITERAL, expecting RETURN or IDENTIFIER or RSQBRACK ERROR:HDLParsers:164 - z:/camurati/esercitazione_1/Carry_lookahead_logic.vhd Line 34. parse error, unexpected INTEGER_LITERAL, expecting RETURN or IDENTIFIER or RSQBRACK ERROR:HDLParsers:164 - z:/camurati/esercitazione_1/Carry_lookahead_logic.vhd Line 35. parse error, unexpected INTEGER_LITERAL, expecting RETURN or IDENTIFIER or RSQBRACK ERROR:HDLParsers:164 - z:/camurati/esercitazione_1/Carry_lookahead_logic.vhd Line 36. parse error, unexpected INTEGER_LITERAL, expecting RETURN or IDENTIFIER or RSQBRACK ERROR: XST failed Process "Check Syntax" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "Check Syntax". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file z:/camurati/esercitazione_1/Carry_lookahead_logic.vhd in Library work. Entity (Architecture ) compiled. Completed process "Check Syntax". Project Navigator Auto-Make Log File ------------------------------------- Started process "Create Schematic Symbol". Release 6.3i - sch2sym G.35 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. Completed process "Create Schematic Symbol". Project Navigator Auto-Make Log File ------------------------------------- Started process "Check Syntax". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file z:/camurati/esercitazione_1/Carry_lookahead_logic.vhd in Library work. Architecture behavioral of Entity carry_lookahead_logic is up to date. Completed process "Check Syntax". Project Navigator Auto-Make Log File ------------------------------------- Started process "Create Schematic Symbol". Compiling vhdl file z:/camurati/esercitazione_1/Carry_lookahead_logic.vhd in Library work. Entity (Architecture ) compiled. tdtfi(vhdl) completed successfully. Release 6.3i - spl2sym G.35 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. Completed process "Create Schematic Symbol". Project Navigator Auto-Make Log File ------------------------------------- Started process "View VHDL Functional Model". Release 6.3i - sch2vhdl G.35 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. ERROR:DesignEntry:101 - Destination branch of bus tap at (1488 1696, 1488 1792) is not part of the source branch of the bus tap. ERROR:DesignEntry:101 - Destination branch of bus tap at (1664 1696, 1664 1792) is not part of the source branch of the bus tap. ERROR:DesignEntry:101 - Destination branch of bus tap at (1312 1696, 1312 1792) is not part of the source branch of the bus tap. ERROR:DesignEntry:101 - Destination branch of bus tap at (1840 1696, 1840 1792) is not part of the source branch of the bus tap. ERROR:DesignEntry:10 - Net "C(0)" is a bit bus member name, but there is no corresponding bit bus. ERROR:DesignEntry:10 - Net "C(1)" is a bit bus member name, but there is no corresponding bit bus. ERROR:DesignEntry:10 - Net "C(2)" is a bit bus member name, but there is no corresponding bit bus. ERROR:DesignEntry:10 - Net "C(3)" is a bit bus member name, but there is no corresponding bit bus. WARNING:DesignEntry:16 - Bus "XLXN_7(3:0)" is connected to source pins and/or IO ports while there is no load pin connected to it WARNING:DesignEntry:11 - Net "C(0)" is connected to load pins and/or IO Port, but there is no source pin or IO Port connected to it WARNING:DesignEntry:11 - Net "C(1)" is connected to load pins and/or IO Port, but there is no source pin or IO Port connected to it WARNING:DesignEntry:11 - Net "C(2)" is connected to load pins and/or IO Port, but there is no source pin or IO Port connected to it WARNING:DesignEntry:11 - Net "C(3)" is connected to load pins and/or IO Port, but there is no source pin or IO Port connected to it WARNING:DesignEntry:13 - Net "S(4)" is connected to source pins and/or IO ports while there is no load pin connected to it WARNING:DesignEntry:13 - Net "S(3)" is connected to source pins and/or IO ports while there is no load pin connected to it WARNING:DesignEntry:13 - Net "S(2)" is connected to source pins and/or IO ports while there is no load pin connected to it WARNING:DesignEntry:13 - Net "S(1)" is connected to source pins and/or IO ports while there is no load pin connected to it WARNING:DesignEntry:13 - Net "S(0)" is connected to source pins and/or IO ports while there is no load pin connected to it Error: Process "View VHDL Functional Model" did not complete. Project Navigator Auto-Make Log File ------------------------------------- Started process "View VHDL Functional Model". Release 6.3i - sch2vhdl G.35 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. WARNING:DesignEntry:13 - Net "S(4)" is connected to source pins and/or IO ports while there is no load pin connected to it WARNING:DesignEntry:13 - Net "S(3)" is connected to source pins and/or IO ports while there is no load pin connected to it WARNING:DesignEntry:13 - Net "S(2)" is connected to source pins and/or IO ports while there is no load pin connected to it WARNING:DesignEntry:13 - Net "S(1)" is connected to source pins and/or IO ports while there is no load pin connected to it WARNING:DesignEntry:13 - Net "S(0)" is connected to source pins and/or IO ports while there is no load pin connected to it DRC Check completed: No Error found. Vhdl netlist file generated. Completed process "View VHDL Functional Model". Project Navigator Auto-Make Log File ------------------------------------- Started process "View VHDL Functional Model". Release 6.3i - sch2vhdl G.35 Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. DRC Check completed: No Error found. Vhdl netlist file generated. Completed process "View VHDL Functional Model". Project Navigator Auto-Make Log File ------------------------------------- Launching Application for process "Generate Expected Simulation Results". Reading c:/program files/Modeltech_xe_starter/win32xoem/../tcl/vsim/pref.tcl # 5.8c # do lookahead_tester.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.8c Compiler 2004.03 Mar 26 2004 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity carry_lookahead_logic # -- Compiling architecture behavioral of carry_lookahead_logic # Model Technology ModelSim XE II vcom 5.8c Compiler 2004.03 Mar 26 2004 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package numeric_std # -- Loading package vital_timing # -- Loading package vcomponents # -- Compiling entity carry_lookahead_adder # -- Compiling architecture behavioral of carry_lookahead_adder # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading entity carry_lookahead_logic # -- Loading entity xor3 # -- Loading entity and2 # Model Technology ModelSim XE II vcom 5.8c Compiler 2004.03 Mar 26 2004 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package numeric_std # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity lookahead_tester # -- Compiling architecture testbench_arch of lookahead_tester # -- Loading package vital_timing # -- Loading package vcomponents # -- Loading entity carry_lookahead_adder # -- Compiling configuration carry_lookahead_adder_cfg # -- Loading entity lookahead_tester # -- Loading architecture testbench_arch of lookahead_tester # vsim -lib work -t 1ps lookahead_tester # Loading c:\program files\Modeltech_xe_starter\win32xoem/../std.standard # Loading c:\program files\Modeltech_xe_starter\win32xoem/../ieee.std_logic_1164(body) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../ieee.numeric_std(body) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../std.textio(body) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../ieee.std_logic_textio(body) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../ieee.vital_timing(body) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../xilinx/vhdl/unisim.vcomponents # Loading work.lookahead_tester(testbench_arch) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../ieee.std_logic_arith(body) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../ieee.std_logic_unsigned(body) # Loading work.carry_lookahead_adder(behavioral) # Loading work.carry_lookahead_logic(behavioral) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../xilinx/vhdl/unisim.xor3(xor3_v) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../xilinx/vhdl/unisim.and2(and2_v) # ** Failure: Success! Simulation for annotation completed # Time: 900 ns Iteration: 0 Process: /lookahead_tester/line__75 File: lookahead_tester.ant # Break at lookahead_tester.ant line 115 # Stopped at lookahead_tester.ant line 115 Project Navigator Auto-Make Log File ------------------------------------- Launching Application for process "Generate Expected Simulation Results". Reading c:/program files/Modeltech_xe_starter/win32xoem/../tcl/vsim/pref.tcl # 5.8c # do lookahead_tester.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.8c Compiler 2004.03 Mar 26 2004 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity carry_lookahead_logic # -- Compiling architecture behavioral of carry_lookahead_logic # ** Error: Carry_lookahead_logic.vhd(19): near "=": expecting: ';' # ** Error: Carry_lookahead_logic.vhd(20): near "=": expecting: ';' # ** Error: c:/program files/Modeltech_xe_starter/win32xoem/vcom failed. # Executing ONERROR command at macro ./lookahead_tester.ado line 10 ERROR: VSim failed to simulate annotated testbench Project Navigator Auto-Make Log File ------------------------------------- Launching Application for process "Generate Expected Simulation Results". Reading c:/program files/Modeltech_xe_starter/win32xoem/../tcl/vsim/pref.tcl # 5.8c # do lookahead_tester.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.8c Compiler 2004.03 Mar 26 2004 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity carry_lookahead_logic # -- Compiling architecture behavioral of carry_lookahead_logic # Model Technology ModelSim XE II vcom 5.8c Compiler 2004.03 Mar 26 2004 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package numeric_std # -- Loading package vital_timing # -- Loading package vcomponents # -- Compiling entity carry_lookahead_adder # -- Compiling architecture behavioral of carry_lookahead_adder # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading entity carry_lookahead_logic # -- Loading entity xor3 # -- Loading entity and2 # Model Technology ModelSim XE II vcom 5.8c Compiler 2004.03 Mar 26 2004 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package numeric_std # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity lookahead_tester # -- Compiling architecture testbench_arch of lookahead_tester # -- Loading package vital_timing # -- Loading package vcomponents # -- Loading entity carry_lookahead_adder # -- Compiling configuration carry_lookahead_adder_cfg # -- Loading entity lookahead_tester # -- Loading architecture testbench_arch of lookahead_tester # vsim -lib work -t 1ps lookahead_tester # Loading c:\program files\Modeltech_xe_starter\win32xoem/../std.standard # Loading c:\program files\Modeltech_xe_starter\win32xoem/../ieee.std_logic_1164(body) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../ieee.numeric_std(body) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../std.textio(body) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../ieee.std_logic_textio(body) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../ieee.vital_timing(body) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../xilinx/vhdl/unisim.vcomponents # Loading work.lookahead_tester(testbench_arch) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../ieee.std_logic_arith(body) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../ieee.std_logic_unsigned(body) # Loading work.carry_lookahead_adder(behavioral) # Loading work.carry_lookahead_logic(behavioral) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../xilinx/vhdl/unisim.xor3(xor3_v) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../xilinx/vhdl/unisim.and2(and2_v) # ** Failure: Success! Simulation for annotation completed # Time: 900 ns Iteration: 0 Process: /lookahead_tester/line__75 File: lookahead_tester.ant # Break at lookahead_tester.ant line 115 # Stopped at lookahead_tester.ant line 115 Project Navigator Auto-Make Log File ------------------------------------- Launching Application for process "Generate Expected Simulation Results". Reading c:/program files/Modeltech_xe_starter/win32xoem/../tcl/vsim/pref.tcl # 5.8c # do carry_lookahead_tester.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.8c Compiler 2004.03 Mar 26 2004 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity carry_lookahead_logic # -- Compiling architecture behavioral of carry_lookahead_logic # Model Technology ModelSim XE II vcom 5.8c Compiler 2004.03 Mar 26 2004 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package numeric_std # -- Loading package vital_timing # -- Loading package vcomponents # -- Compiling entity carry_lookahead_adder # -- Compiling architecture behavioral of carry_lookahead_adder # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading entity carry_lookahead_logic # -- Loading entity xor3 # -- Loading entity and2 # Model Technology ModelSim XE II vcom 5.8c Compiler 2004.03 Mar 26 2004 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package numeric_std # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity carry_lookahead_tester # -- Compiling architecture testbench_arch of carry_lookahead_tester # -- Loading package vital_timing # -- Loading package vcomponents # -- Loading entity carry_lookahead_adder # -- Compiling configuration carry_lookahead_adder_cfg # -- Loading entity carry_lookahead_tester # -- Loading architecture testbench_arch of carry_lookahead_tester # vsim -lib work -t 1ps carry_lookahead_tester # Loading c:\program files\Modeltech_xe_starter\win32xoem/../std.standard # Loading c:\program files\Modeltech_xe_starter\win32xoem/../ieee.std_logic_1164(body) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../ieee.numeric_std(body) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../std.textio(body) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../ieee.std_logic_textio(body) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../ieee.vital_timing(body) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../xilinx/vhdl/unisim.vcomponents # Loading work.carry_lookahead_tester(testbench_arch) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../ieee.std_logic_arith(body) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../ieee.std_logic_unsigned(body) # Loading work.carry_lookahead_adder(behavioral) # Loading work.carry_lookahead_logic(behavioral) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../xilinx/vhdl/unisim.xor3(xor3_v) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../xilinx/vhdl/unisim.and2(and2_v) # ** Failure: Success! Simulation for annotation completed # Time: 1250 ns Iteration: 0 Process: /carry_lookahead_tester/line__75 File: carry_lookahead_tester.ant # Break at carry_lookahead_tester.ant line 125 # Stopped at carry_lookahead_tester.ant line 125 Project Navigator Auto-Make Log File ------------------------------------- Launching Application for process "Generate Expected Simulation Results". Reading c:/program files/Modeltech_xe_starter/win32xoem/../tcl/vsim/pref.tcl # 5.8c # do carry_lookahead_tester.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.8c Compiler 2004.03 Mar 26 2004 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity carry_lookahead_logic # -- Compiling architecture behavioral of carry_lookahead_logic # Model Technology ModelSim XE II vcom 5.8c Compiler 2004.03 Mar 26 2004 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package numeric_std # -- Loading package vital_timing # -- Loading package vcomponents # -- Compiling entity carry_lookahead_adder # -- Compiling architecture behavioral of carry_lookahead_adder # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading entity carry_lookahead_logic # -- Loading entity xor3 # -- Loading entity and2 # Model Technology ModelSim XE II vcom 5.8c Compiler 2004.03 Mar 26 2004 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package numeric_std # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity carry_lookahead_tester # -- Compiling architecture testbench_arch of carry_lookahead_tester # -- Loading package vital_timing # -- Loading package vcomponents # -- Loading entity carry_lookahead_adder # -- Compiling configuration carry_lookahead_adder_cfg # -- Loading entity carry_lookahead_tester # -- Loading architecture testbench_arch of carry_lookahead_tester # vsim -lib work -t 1ps carry_lookahead_tester # Loading c:\program files\Modeltech_xe_starter\win32xoem/../std.standard # Loading c:\program files\Modeltech_xe_starter\win32xoem/../ieee.std_logic_1164(body) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../ieee.numeric_std(body) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../std.textio(body) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../ieee.std_logic_textio(body) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../ieee.vital_timing(body) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../xilinx/vhdl/unisim.vcomponents # Loading work.carry_lookahead_tester(testbench_arch) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../ieee.std_logic_arith(body) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../ieee.std_logic_unsigned(body) # Loading work.carry_lookahead_adder(behavioral) # Loading work.carry_lookahead_logic(behavioral) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../xilinx/vhdl/unisim.xor3(xor3_v) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../xilinx/vhdl/unisim.and2(and2_v) # ** Failure: Success! Simulation for annotation completed # Time: 1250 ns Iteration: 0 Process: /carry_lookahead_tester/line__75 File: carry_lookahead_tester.ant # Break at carry_lookahead_tester.ant line 125 # Stopped at carry_lookahead_tester.ant line 125 Project Navigator Auto-Make Log File ------------------------------------- Launching Application for process "Generate Expected Simulation Results". Reading c:/program files/Modeltech_xe_starter/win32xoem/../tcl/vsim/pref.tcl # 5.8c # do carry_lookahead_tester.ado listening on address 127.0.0.1 port 1200 # ** Warning: (vlib-34) Library already exists at "work". # resume # Model Technology ModelSim XE II vcom 5.8c Compiler 2004.03 Mar 26 2004 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Compiling entity carry_lookahead_logic # -- Compiling architecture behavioral of carry_lookahead_logic # Model Technology ModelSim XE II vcom 5.8c Compiler 2004.03 Mar 26 2004 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package numeric_std # -- Loading package vital_timing # -- Loading package vcomponents # -- Compiling entity carry_lookahead_adder # -- Compiling architecture behavioral of carry_lookahead_adder # -- Loading package std_logic_arith # -- Loading package std_logic_unsigned # -- Loading entity carry_lookahead_logic # -- Loading entity xor3 # -- Loading entity and2 # Model Technology ModelSim XE II vcom 5.8c Compiler 2004.03 Mar 26 2004 # -- Loading package standard # -- Loading package std_logic_1164 # -- Loading package numeric_std # -- Loading package textio # -- Loading package std_logic_textio # -- Compiling entity carry_lookahead_tester # -- Compiling architecture testbench_arch of carry_lookahead_tester # -- Loading package vital_timing # -- Loading package vcomponents # -- Loading entity carry_lookahead_adder # -- Compiling configuration carry_lookahead_adder_cfg # -- Loading entity carry_lookahead_tester # -- Loading architecture testbench_arch of carry_lookahead_tester # vsim -lib work -t 1ps carry_lookahead_tester # Loading c:\program files\Modeltech_xe_starter\win32xoem/../std.standard # Loading c:\program files\Modeltech_xe_starter\win32xoem/../ieee.std_logic_1164(body) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../ieee.numeric_std(body) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../std.textio(body) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../ieee.std_logic_textio(body) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../ieee.vital_timing(body) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../xilinx/vhdl/unisim.vcomponents # Loading work.carry_lookahead_tester(testbench_arch) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../ieee.std_logic_arith(body) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../ieee.std_logic_unsigned(body) # Loading work.carry_lookahead_adder(behavioral) # Loading work.carry_lookahead_logic(behavioral) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../xilinx/vhdl/unisim.xor3(xor3_v) # Loading c:\program files\Modeltech_xe_starter\win32xoem/../xilinx/vhdl/unisim.and2(and2_v) # ** Failure: Success! Simulation for annotation completed # Time: 1450 ns Iteration: 0 Process: /carry_lookahead_tester/line__75 File: carry_lookahead_tester.ant # Break at carry_lookahead_tester.ant line 129 # Stopped at carry_lookahead_tester.ant line 129 Project Navigator Auto-Make Log File ------------------------------------- Started process "Synthesize". ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file z:/camurati/esercitazione_1/Carry_lookahead_logic.vhd in Library work. Entity (Architecture ) compiled. Compiling vhdl file z:/camurati/esercitazione_1/Carry_lookahead_adder.vhf in Library work. Architecture behavioral of Entity carry_lookahead_adder is up to date. ========================================================================= * HDL Analysis * ========================================================================= Analyzing Entity (Architecture ). Entity analyzed. Unit generated. Analyzing Entity (Architecture ). WARNING:Xst:819 - z:/camurati/esercitazione_1/Carry_lookahead_logic.vhd line 23: The following signals are missing in the process sensitivity list: Enable. Entity analyzed. Unit generated. ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is z:/camurati/esercitazione_1/Carry_lookahead_logic.vhd. WARNING:Xst:737 - Found 1-bit latch for signal . WARNING:Xst:737 - Found 1-bit latch for signal . WARNING:Xst:737 - Found 1-bit latch for signal . WARNING:Xst:737 - Found 1-bit latch for signal . WARNING:Xst:737 - Found 1-bit latch for signal . WARNING:Xst:737 - Found 1-bit latch for signal . WARNING:Xst:737 - Found 1-bit latch for signal . WARNING:Xst:737 - Found 1-bit latch for signal . Unit synthesized. Synthesizing Unit . Related source file is z:/camurati/esercitazione_1/Carry_lookahead_adder.vhf. Unit synthesized. ========================================================================= * Advanced HDL Synthesis * ========================================================================= Advanced RAM inference ... Advanced multiplier inference ... Advanced Registered AddSub inference ... Dynamic shift register inference ... ========================================================================= HDL Synthesis Report Macro Statistics # Latches : 8 1-bit latch : 8 ========================================================================= ========================================================================= * Low Level Synthesis * ========================================================================= Optimizing unit ... Optimizing unit ... Loading device for application Xst from file '3s200.nph' in environment C:/Program Files/Xilinx. Mapping all equations... Building and optimizing final netlist ... Found area constraint ratio of 100 (+ 5) on block carry_lookahead_adder, actual ratio is 0. ========================================================================= * Final Report * ========================================================================= Device utilization summary: --------------------------- Selected Device : 3s200ft256-4 Number of Slices: 9 out of 1920 0% Number of Slice Flip Flops: 8 out of 3840 0% Number of 4 input LUTs: 16 out of 3840 0% Number of bonded IOBs: 14 out of 173 8% Number of GCLKs: 1 out of 8 12% ========================================================================= TIMING REPORT Clock Information: ------------------ -----------------------------------+------------------------+-------+ Clock Signal | Clock buffer(FF name) | Load | -----------------------------------+------------------------+-------+ Enable | BUFGP | 8 | -----------------------------------+------------------------+-------+ Timing Summary: --------------- Speed Grade: -4 Minimum period: No path found Minimum input arrival time before clock: 3.261ns Maximum output required time after clock: 10.265ns Maximum combinational path delay: 11.614ns ========================================================================= Completed process "Synthesize". Started process "Translate". Command Line: ngdbuild -intstyle ise -dd z:\camurati\esercitazione_1/_ngo -i -p xc3s200-ft256-4 carry_lookahead_adder.ngc carry_lookahead_adder.ngd Reading NGO file "z:/camurati/esercitazione_1/carry_lookahead_adder.ngc" ... Reading component libraries for design expansion... Checking timing specifications ... Checking expanded design ... NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0 Total memory usage is 38140 kilobytes Writing NGD file "carry_lookahead_adder.ngd" ... Writing NGDBUILD log file "carry_lookahead_adder.bld"... NGDBUILD done. Completed process "Translate". Started process "Map". Using target part "3s200ft256-4". Removing unused or disabled logic... Running cover... Running directed packing... Running delay-based LUT packing... Running related packing... Design Summary: Number of errors: 0 Number of warnings: 1 Logic Utilization: Number of Slice Latches: 8 out of 3,840 1% Number of 4 input LUTs: 18 out of 3,840 1% Logic Distribution: Number of occupied Slices: 9 out of 1,920 1% Number of Slices containing only related logic: 9 out of 9 100% Number of Slices containing unrelated logic: 0 out of 9 0% *See NOTES below for an explanation of the effects of unrelated logic Total Number of 4 input LUTs: 18 out of 3,840 1% Number of bonded IOBs: 15 out of 173 8% Number of GCLKs: 1 out of 8 12% Total equivalent gate count for design: 151 Additional JTAG gate count for IOBs: 720 Peak Memory Usage: 67 MB NOTES: Related logic is defined as being logic that shares connectivity - e.g. two LUTs are "related" if they share common inputs. When assembling slices, Map gives priority to combine logic that is related. Doing so results in the best timing performance. Unrelated logic shares no connectivity. Map will only begin packing unrelated logic into a slice once 99% of the slices are occupied through related logic packing. Note that once logic distribution reaches the 99% level through related logic packing, this does not mean the device is completely utilized. Unrelated logic packing will then begin, continuing until all usable LUTs and FFs are occupied. Depending on your timing budget, increased levels of unrelated logic packing may adversely affect the overall timing performance of your design. Mapping completed. See MAP report file "carry_lookahead_adder_map.mrp" for details. Completed process "Map". Mapping Module carry_lookahead_adder . . . MAP command line: map -intstyle ise -p xc3s200-ft256-4 -cm area -pr b -k 4 -c 100 -tx off -o carry_lookahead_adder_map.ncd carry_lookahead_adder.ngd carry_lookahead_adder.pcf Mapping Module carry_lookahead_adder: DONE Started process "Place & Route". Constraints file: carry_lookahead_adder.pcf Loading device database for application Par from file "carry_lookahead_adder_map.ncd". "carry_lookahead_adder" is an NCD, version 2.38, device xc3s200, package ft256, speed -4 Loading device for application Par from file '3s200.nph' in environment C:/Program Files/Xilinx. Device speed data version: PRODUCTION 1.32 2004-06-25. Resolving physical constraints. Finished resolving physical constraints. Device utilization summary: Number of External IOBs 15 out of 173 8% Number of LOCed External IOBs 0 out of 15 0% Number of Slices 9 out of 1920 1% Number of BUFGMUXs 1 out of 8 12% Overall effort level (-ol): Standard (set by user) Placer effort level (-pl): Standard (set by user) Placer cost table entry (-t): 1 Router effort level (-rl): Standard (set by user) Phase 1.1 Phase 1.1 (Checksum:9896ca) REAL time: 0 secs . Phase 3.3 Phase 3.3 (Checksum:1c9c37d) REAL time: 2 secs Phase 4.5 Phase 4.5 (Checksum:26259fc) REAL time: 2 secs Phase 5.8 . Phase 5.8 (Checksum:993ce7) REAL time: 2 secs Phase 6.5 Phase 6.5 (Checksum:39386fa) REAL time: 2 secs Phase 7.18 Phase 7.18 (Checksum:42c1d79) REAL time: 2 secs Writing design to file carry_lookahead_adder.ncd. Total REAL time to Placer completion: 2 secs Total CPU time to Placer completion: 0 secs Phase 1: 66 unrouted; REAL time: 2 secs Phase 2: 61 unrouted; REAL time: 2 secs Phase 3: 28 unrouted; REAL time: 2 secs Phase 4: 0 unrouted; REAL time: 2 secs Total REAL time to Router completion: 2 secs Total CPU time to Router completion: 1 secs Generating "par" statistics. ************************** Generating Clock Report ************************** +-------------------------+----------+------+------+------------+-------------+ | Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)| +-------------------------+----------+------+------+------------+-------------+ | Enable_BUFGP | BUFGMUX0| No | 11 | 0.000 | 1.011 | +-------------------------+----------+------+------+------------+-------------+ Generating Pad Report. All signals are completely routed. Total REAL time to PAR completion: 6 secs Total CPU time to PAR completion: 1 secs Peak Memory Usage: 56 MB Placement: Completed - No errors found. Routing: Completed - No errors found. Writing design to file carry_lookahead_adder.ncd. PAR done. Completed process "Place & Route". Started process "Generate Post-Place & Route Static Timing". Analysis completed Fri Mar 09 08:53:59 2007 -------------------------------------------------------------------------------- Generating Report ... Completed process "Generate Post-Place & Route Static Timing". Place & Route Module carry_lookahead_adder . . . PAR command line: par -w -intstyle ise -ol std -t 1 carry_lookahead_adder_map.ncd carry_lookahead_adder.ncd carry_lookahead_adder.pcf PAR completed successfully Started process "Generate Post-Place & Route Simulation Model". Completed process "Generate Post-Place & Route Simulation Model". Compiling vhdl file z:/camurati/esercitazione_1/carry_lookahead_adder.vhf in Library work. Entity (Architecture ) compiled. Project Navigator Auto-Make Log File ------------------------------------- Compiling vhdl file z:/camurati/esercitazione_1/carry_lookahead_adder.vhf in Library work. Entity (Architecture ) compiled. Project Navigator Auto-Make Log File ------------------------------------- Started process "Translate". Command Line: ngdbuild -intstyle ise -dd z:\camurati\esercitazione_1/_ngo -uc carry_lookahead_adder.ucf -p xc3s200-ft256-4 carry_lookahead_adder.ngc carry_lookahead_adder.ngd Reading NGO file "z:/camurati/esercitazione_1/carry_lookahead_adder.ngc" ... Reading component libraries for design expansion... Annotating constraints to design from file "carry_lookahead_adder.ucf" ... Checking timing specifications ... Checking expanded design ... NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0 Total memory usage is 39164 kilobytes Writing NGD file "carry_lookahead_adder.ngd" ... Writing NGDBUILD log file "carry_lookahead_adder.bld"... NGDBUILD done. Completed process "Translate". Started process "Map". Using target part "3s200ft256-4". Removing unused or disabled logic... Running cover... Running directed packing... Running delay-based LUT packing... Running related packing... Design Summary: Number of errors: 0 Number of warnings: 1 Logic Utilization: Number of Slice Latches: 8 out of 3,840 1% Number of 4 input LUTs: 18 out of 3,840 1% Logic Distribution: Number of occupied Slices: 9 out of 1,920 1% Number of Slices containing only related logic: 9 out of 9 100% Number of Slices containing unrelated logic: 0 out of 9 0% *See NOTES below for an explanation of the effects of unrelated logic Total Number of 4 input LUTs: 18 out of 3,840 1% Number of bonded IOBs: 15 out of 173 8% Number of GCLKs: 1 out of 8 12% Total equivalent gate count for design: 151 Additional JTAG gate count for IOBs: 720 Peak Memory Usage: 67 MB NOTES: Related logic is defined as being logic that shares connectivity - e.g. two LUTs are "related" if they share common inputs. When assembling slices, Map gives priority to combine logic that is related. Doing so results in the best timing performance. Unrelated logic shares no connectivity. Map will only begin packing unrelated logic into a slice once 99% of the slices are occupied through related logic packing. Note that once logic distribution reaches the 99% level through related logic packing, this does not mean the device is completely utilized. Unrelated logic packing will then begin, continuing until all usable LUTs and FFs are occupied. Depending on your timing budget, increased levels of unrelated logic packing may adversely affect the overall timing performance of your design. Mapping completed. See MAP report file "carry_lookahead_adder_map.mrp" for details. Completed process "Map". Mapping Module carry_lookahead_adder . . . MAP command line: map -intstyle ise -p xc3s200-ft256-4 -cm area -pr b -k 4 -c 100 -tx off -o carry_lookahead_adder_map.ncd carry_lookahead_adder.ngd carry_lookahead_adder.pcf Mapping Module carry_lookahead_adder: DONE Started process "Place & Route". Constraints file: carry_lookahead_adder.pcf Loading device database for application Par from file "carry_lookahead_adder_map.ncd". "carry_lookahead_adder" is an NCD, version 2.38, device xc3s200, package ft256, speed -4 Loading device for application Par from file '3s200.nph' in environment C:/Program Files/Xilinx. Device speed data version: PRODUCTION 1.32 2004-06-25. Resolving physical constraints. Finished resolving physical constraints. Device utilization summary: Number of External IOBs 15 out of 173 8% Number of LOCed External IOBs 15 out of 15 100% Number of Slices 9 out of 1920 1% Number of BUFGMUXs 1 out of 8 12% Overall effort level (-ol): Standard (set by user) Placer effort level (-pl): Standard (set by user) Placer cost table entry (-t): 1 Router effort level (-rl): Standard (set by user) Phase 1.1 Phase 1.1 (Checksum:9896ca) REAL time: 0 secs ..... ......... Phase 3.8 . Phase 3.8 (Checksum:98ba5b) REAL time: 0 secs Phase 4.5 Phase 4.5 (Checksum:26259fc) REAL time: 0 secs Phase 5.18 Phase 5.18 (Checksum:2faf07b) REAL time: 0 secs Writing design to file carry_lookahead_adder.ncd. Total REAL time to Placer completion: 0 secs Total CPU time to Placer completion: 0 secs Phase 1: 66 unrouted; REAL time: 0 secs Phase 2: 62 unrouted; REAL time: 0 secs Phase 3: 22 unrouted; REAL time: 0 secs Phase 4: 0 unrouted; REAL time: 0 secs Total REAL time to Router completion: 0 secs Total CPU time to Router completion: 0 secs Generating "par" statistics. ************************** Generating Clock Report ************************** +-------------------------+----------+------+------+------------+-------------+ | Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)| +-------------------------+----------+------+------+------------+-------------+ | Enable_BUFGP | BUFGMUX0| No | 11 | 0.001 | 1.012 | +-------------------------+----------+------+------+------------+-------------+ Generating Pad Report. All signals are completely routed. Total REAL time to PAR completion: 5 secs Total CPU time to PAR completion: 1 secs Peak Memory Usage: 56 MB Placement: Completed - No errors found. Routing: Completed - No errors found. Writing design to file carry_lookahead_adder.ncd. PAR done. Completed process "Place & Route". Started process "Generate Post-Place & Route Static Timing". Analysis completed Fri Mar 09 09:12:02 2007 -------------------------------------------------------------------------------- Generating Report ... Completed process "Generate Post-Place & Route Static Timing". Place & Route Module carry_lookahead_adder . . . PAR command line: par -w -intstyle ise -ol std -t 1 carry_lookahead_adder_map.ncd carry_lookahead_adder.ncd carry_lookahead_adder.pcf PAR completed successfully Started process "Generate Programming File". Completed process "Generate Programming File".