library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity Carry_lookahead_logic is
Port(Enable,Carry_in: in std_logic;A,B:in std_logic_vector(3 downto 0);C:out std_logic_vector(3 downto 0);Carry_out:out std_logic);
end Carry_lookahead_logic;

architecture Behavioral of Carry_lookahead_logic is

signal carry: std_logic_vector(3 downto 0):="0000";
signal co:std_logic:='0';
signal P:std_logic_vector(3 downto 0):="0000";
signal G:std_logic_vector(3 downto 0):="0000";

begin
process(Carry_in,A,B)
begin
if Enable='0' then
	co<='0';
	carry<="0000";
else
	carry(0)<=Carry_in;
	for I in 0 to 3 loop
		G(I)<=A(I) and B(I);
		P(I)<=A(I) or B(I);
	end loop;
	carry(1)<=G(0) or (carry(0) and P(0));
	carry(2)<=G(1) or (G(0) and P(1)) or (carry(0) and P(0) and P(1));
	carry(3)<=G(2) or (G(1) and P(2)) or (G(0) and P(1) and P(2)) or (carry(0) and P(0) and P(1) and P(2));
	co<=G(3) or (G(2) and P(3)) or (G(1) and P(2) and P(3)) or (G(0) and P(1) and P(2) and P(3)) or (carry(0) and P(0) and P(1) and P(2) and P(3));	
end if;
end process;
C<=carry;
Carry_out<=co;
end Behavioral;